Inventor · disambiguated record
Krishna Belkhale
Also filed as: BELKHALE KRISHNA · BELKHALE KRISHNA P · BELKHALE KRISHNA PRASAD
16 granted patents·414 citations·filing 1994–2020
94Inventor score
Technology areasG06F
Top patents by PatentIndex Score
16 records- 0196US8788995B1System and method for guiding remedial transformations of a circuit design defined by physical implementation data to reduce needed physical corrections for detected timing violations in the circuit designCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Jul 22, 2014·55 cites·16 claims
- 0294US8745561B1System and method for common path pessimism reduction in timing analysis to guide remedial transformations of a circuit designCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Jun 3, 2014·36 cites·20 claims
- 0382US11144698B1Method, system, and product for an improved approach to placement and optimization in a physical design flowCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Oct 12, 2021·2 cites·20 claims
- 0482US7356451B2Assertion handling for timing model extractionCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Apr 8, 2008·30 cites·61 claims
- 0582US6928630B2Timing model extraction by timing graph reductionCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Aug 9, 2005·31 cites·53 claims
- 0679US10133842B1Methods, systems, and articles of manufacture for multi-mode, multi-corner physical optimization of electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Nov 20, 2018·4 cites·22 claims
- 0778US5636372ANetwork timing analysis method which eliminates timing variations between signals traversing a common circuit pathIBM·Filed 1994·Granted Jun 3, 1997·94 cites·7 claims
- 0872US6023566ACluster matching for circuit implementationCADENCE DESIGN SYSTEMS·Filed 1997·Granted Feb 8, 2000·67 cites·20 claims
- 0968US11188696B1Method, system, and product for deferred merge based method for graph based analysis pessimism reductionCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Nov 30, 2021·1 cites·20 claims
- 1065US7797649B1Method and system for implementing an analytical wirelength formulationCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Sep 14, 2010·3 cites·26 claims
- 1160US5991524ACluster determination for circuit implementationCADENCE DESIGN SYSTEMS·Filed 1997·Granted Nov 23, 1999·39 cites·4 claims
- 1258US6543037B1Delay estimation for restructuring the technology independent circuitCADENCE DESIGN SYSTEMS INC·Filed 1999·Granted Apr 1, 2003·30 cites·48 claims
- 1352US7107556B1Method and system for implementing an analytical wirelength formulation for unavailability of routing directionsCADENCE DESIGN SYSTEMS INC·Filed 2004·Granted Sep 12, 2006·3 cites·18 claims
- 1448US7168053B1Method and system for implementing an analytical wirelength formulationCADENCE DESIGN SYSTEMS INC·Filed 2004·Granted Jan 23, 2007·1 cites·20 claims
- 1538US6401231B1Method and apparatus for performing both negative and positive slack time budgeting and for determining a definite required constraint during integrated circuit designCADENCE DESIGN SYSTEMS INC·Filed 1997·Granted Jun 4, 2002·12 cites·9 claims
- 1633US6672776B1Delay estimation for restructuringCADENCE DESIGN SYSTEMS·Filed 1997·Granted Jan 6, 2004·6 cites·48 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →