Inventor · disambiguated record
Krishna Vijaya Chakravadhanula
Also filed as: CHAKRAVADHANULA KRISHNA · CHAKRAVADHANULA KRISHNA V · Chakravadhanula Krishna Vijaya
29 granted patents·177 citations·filing 2008–2022
96Inventor score
Files withCADENCE DESIGN SYSTEMS INC23CADENCE DESIGNS SYSTEMS INC2CHAKRAVADHANULA KRISHNA2CHAKRAVADHANULA KRISHNA V1KHURANA RAJESH1
Top patents by PatentIndex Score
29 records- 0197US8904256B1Method and apparatus for low-pin count testing of integrated circuitsCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Dec 2, 2014·35 cites·27 claims
- 0295US8650524B1Method and apparatus for low-pin count testing of integrated circuitsCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Feb 11, 2014·41 cites·24 claims
- 0393US9606179B1Method and system for improving efficiency of XOR-based test compression using an embedded serializer-deserializerCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Mar 28, 2017·7 cites·18 claims
- 0490US9513335B1Method for using XOR trees for physically efficient scan compression and decompression logicCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Dec 6, 2016·5 cites·10 claims
- 0590US9470756B1Method for using sequential decompression logic for VLSI test in a physically efficient constructionCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Oct 18, 2016·5 cites·20 claims
- 0687US12007440B1Systems and methods for scan chain stitchingCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Jun 11, 2024·1 cites·20 claims
- 0787US11947887B1Test-point flop sharing with improved testability in a circuit designCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Apr 2, 2024·1 cites·20 claims
- 0887US9817068B1Method and system for improving efficiency of sequential test compression using overscanCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Nov 14, 2017·4 cites·12 claims
- 0987US9170301B1Hierarchical compaction for test pattern power generationCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Oct 27, 2015·8 cites·30 claims
- 1086US9470754B1Elastic compression-optimizing tester bandwidth with compressed test stimuli using overscan and variable serializationCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Oct 18, 2016·3 cites·20 claims
- 1185US10528689B1Verification process for IJTAG based test pattern migrationCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jan 7, 2020·7 cites·20 claims
- 1285US10331506B1SoC top-level XOR compactor design to efficiently test and diagnose multiple identical coresCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Jun 25, 2019·4 cites·17 claims
- 1382US10996270B1System and method for multiple device diagnostics and failure groupingCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted May 4, 2021·3 cites·20 claims
- 1482US10955470B1Method to improve testability using 2-dimensional exclusive or (XOR) gridsCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Mar 23, 2021·2 cites·9 claims
- 1582US10853100B1Systems and methods for creating learning-based personalized user interfacesCADENCE DESIGNS SYSTEMS INC·Filed 2018·Granted Dec 1, 2020·7 cites·20 claims
- 1682US10775435B1Low-power shift with clock staggeringCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Sep 15, 2020·3 cites·12 claims
- 1782US10325048B1Virtual directory navigation and debugging across multiple test configurations in the same sessionCADENCE DESIGNS SYSTEMS INC·Filed 2016·Granted Jun 18, 2019·5 cites·12 claims
- 1880US9817069B1Method and system for construction of a highly efficient and predictable sequential test decompression logicCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Nov 14, 2017·2 cites·20 claims
- 1977US10761131B1Method for optimally connecting scan segments in two-dimensional compression chainsCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Sep 1, 2020·2 cites·20 claims
- 2077US9470755B1Method for dividing testable logic into a two-dimensional grid for physically efficient scanCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Oct 18, 2016·2 cites·20 claims
- 2177US8296703B1Fault modeling for state retention logicCHAKRAVADHANULA KRISHNA·Filed 2008·Granted Oct 23, 2012·9 cites·26 claims
- 2275US8271226B2Testing state retention logic in low power systemsCHAKRAVADHANULA KRISHNA·Filed 2008·Granted Sep 18, 2012·8 cites·23 claims
- 2372US8615692B1Method and system for analyzing test vectors to determine toggle countsKHURANA RAJESH·Filed 2009·Granted Dec 24, 2013·8 cites·30 claims
- 2467US8296694B1System and method for automated synthesis of circuit wrappersCHAKRAVADHANULA KRISHNA V·Filed 2009·Granted Oct 23, 2012·5 cites·33 claims
- 2561US12307186B1Launch off shift processCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted May 20, 2025·0 cites·18 claims
- 2658US12412014B1IC chip with IC design modification detectionCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Sep 9, 2025·0 cites·20 claims
- 2757US12475288B1Clock-based test-point flop sharing in a circuit designCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Nov 18, 2025·0 cites·20 claims
- 2855US12511462B1Physical awareness of test-point sharing in a circuit designCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Dec 30, 2025·0 cites·20 claims
- 2936US10551435B12D compression-based low power ATPGCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Feb 4, 2020·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →