Inventor · disambiguated record
Kuei-Chang Tsai
Also filed as: TSAI KUEI-CHANG
16 granted patents·3 pending applications·158 citations·filing 1997–2022
92Inventor score
Files withMOSEL VITELIC INC6ADESTO TECHNOLOGIES CORP4PROMOS TECHNOLOGIES INC4ADESTO TECH CORP2DIALOG SEMICONDUCTOR US INC1
Top patents by PatentIndex Score
19 records- 0193US8941089B2Resistive switching devices and methods of formation thereofADESTO TECHNOLOGIES CORP·Filed 2013·Granted Jan 27, 2015·18 cites·15 claims
- 0293US8866122B1Resistive switching devices having a buffer layer and methods of formation thereofLEE WEI TI·Filed 2012·Granted Oct 21, 2014·18 cites·36 claims
- 0388US6566196B1Sidewall protection in fabrication of integrated circuitsMOSEL VITELIC INC·Filed 2002·Granted May 20, 2003·51 cites·9 claims
- 0468US7297628B2Dynamically controllable reduction of vertical contact diameter through adjustment of etch mask stack for dielectric etchPROMOS TECHNOLOGIES INC·Filed 2003·Granted Nov 20, 2007·14 cites·33 claims
- 0567US6336787B1Method for transferring wafers in a semiconductor tape-peeling apparatusMOSEL VITELIC INC·Filed 2000·Granted Jan 8, 2002·13 cites·2 claims
- 0666US6384482B1Method for forming a dielectric layer in a semiconductor device by using etch stop layersMOSEL VITELIC INC·Filed 2001·Granted May 7, 2002·13 cites·8 claims
- 0764US11056646B2Memory device having programmable impedance elements with a common conductor formed below bit linesADESTO TECHNOLOGIES CORP·Filed 2016·Granted Jul 6, 2021·1 cites·17 claims
- 0859US10497868B2Memory elements having conductive cap layers and methods thereforADESTO TECHNOLOGIES CORP·Filed 2017·Granted Dec 3, 2019·1 cites·17 claims
- 0952US9595671B1Methods of fabricating storage elements and structures having edgeless features for programmable layer(s)ADESTO TECH CORP·Filed 2016·Granted Mar 14, 2017·0 cites·17 claims
- 1052US2014293676A1Programmable impedance memory elements and corresponding methodsADESTO TECHNOLOGIES CORP·Filed 2014·Application pending·0 cites
- 1151US9412945B1Storage elements, structures and methods having edgeless features for programmable layer(s)ADESTO TECH CORP·Filed 2013·Granted Aug 9, 2016·0 cites·9 claims
- 1251US6984574B2Cobalt silicide fabrication using protective titaniumMOSEL VITELIC INC·Filed 2002·Granted Jan 10, 2006·3 cites·38 claims
- 1347US2006211255A1Use of multiple etching steps to reduce lateral etch undercutHUANG CHUNCHIEH·Filed 2006·Application pending·0 cites
- 1445US2023086109A1Cbram bottom electrode structuresDIALOG SEMICONDUCTOR US INC·Filed 2022·Application pending·0 cites
- 1544US7375027B2Method of providing contact via to a surfacePROMOS TECHNOLOGIES INC·Filed 2004·Granted May 20, 2008·2 cites·10 claims
- 1643US6117780AChemical mechanical polishing method with in-line thickness detectionMOSEL VITELIC INC·Filed 1999·Granted Sep 12, 2000·14 cites·16 claims
- 1742US6017816AMethod of fabricating A1N anti-reflection coating on metal layerMOSEL VITELIC INC·Filed 1997·Granted Jan 25, 2000·10 cites·13 claims
- 1838US7071115B2Use of multiple etching steps to reduce lateral etch undercutPROMOS TECHNOLOGIES INC·Filed 2004·Granted Jul 4, 2006·0 cites·12 claims
- 1934US7300745B2Use of pedestals to fabricate contact openingsPROMOS TECHNOLOGIES INC·Filed 2004·Granted Nov 27, 2007·0 cites·52 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →