Use of multiple etching steps to reduce lateral etch undercut

Abstract

In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer ( 160 ), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion ( 160 X 2 ) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask ( 420 ) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.

1 . An integrated circuit comprising: 
 a first feature; and    an extension of the fist feature, the extension being formed from the same material as the first feature, the extension being contiguous with the first feature, the extension having a smaller cross sectional area than the first feature.    
   
   
       2 . The integrated circuit of  claim 1  further comprising a semiconductor substrate, and a first structure projecting upward over the semiconductor substrate, the first structure comprising a first sidewall; 
 wherein the first feature overlays the first sidewall of the first structure.    
   
   
       3 . The integrated circuit of  claim 2  wherein the extension of the first feature does not project upward as far as the first feature.  
   
   
       4 . The integrated circuit of  claim 1  wherein the first feature and the extension are sidewall spacers on the first sidewall.  
   
   
       5 . The integrated circuit of  claim 1  wherein the first feature and the extension are conductive.  
   
   
       6 . The integrated circuit of  claim 1  wherein the first structure comprises a conductive line, and the first sidewall is dielectric.  
   
   
       7 . The integrated circuit of  claim 6  wherein the conductive line provides control gates to a plurality of memory cells, the first structure also comprises conductive floating gates of the memory cells, and the first feature is a wordline for the memory cells.