Inventor · disambiguated record
Lalit Bharat
Also filed as: Bharat Lalit
2 granted patents·9 citations·filing 2015–2020
53Inventor score
Files withCADENCE DESIGN SYSTEMS INC2
Top patents by PatentIndex Score
2 records- 0187US9633159B1Method and system for performing distributed timing signoff and optimizationCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Apr 25, 2017·7 cites·30 claims
- 0277US11256837B1Methods, systems, and computer program product for implementing an electronic design with high-capacity design closureCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Feb 22, 2022·2 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →