Inventor · disambiguated record
Lars-Ake Ragnarsson
Also filed as: RAGNARSSON LARS-AKE
20 granted patents·3 pending applications·1,024 citations·filing 2001–2022
95Inventor score
Top patents by PatentIndex Score
23 records- 0197US7579285B2Atomic layer deposition method for depositing a layerIMEC·Filed 2006·Granted Aug 25, 2009·464 cites·37 claims
- 0295US9287273B2Method for manufacturing a semiconductor device comprising transistors each having a different effective work functionIMEC VZW·Filed 2015·Granted Mar 15, 2016·418 cites·12 claims
- 0393US11367662B2Semiconductor devices and methods of forming the sameIMEC VZW·Filed 2020·Granted Jun 21, 2022·3 cites·17 claims
- 0492US6852575B2Method of forming lattice-matched structure on silicon and structure formed therebyIBM·Filed 2001·Granted Feb 8, 2005·43 cites·47 claims
- 0591US10607896B2Method of forming gate of semiconductor device and semiconductor device having sameIMEC VZW·Filed 2017·Granted Mar 31, 2020·9 cites·17 claims
- 0689US7923743B2Semiconductor structure including mixed rare earth oxide formed on siliconIBM·Filed 2009·Granted Apr 12, 2011·9 cites·7 claims
- 0783US7169674B2Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrierIBM·Filed 2005·Granted Jan 30, 2007·9 cites·20 claims
- 0881US6831339B2Aluminum nitride and aluminum oxide/aluminum nitride heterostructure gate dielectric stack based field effect transistors and method for forming sameIBM·Filed 2001·Granted Dec 14, 2004·24 cites·10 claims
- 0980US7432550B2Semiconductor structure including mixed rare earth oxide formed on siliconIBM·Filed 2004·Granted Oct 7, 2008·16 cites·22 claims
- 1079US7648864B2Semiconductor structure including mixed rare earth oxide formed on siliconIBM·Filed 2008·Granted Jan 19, 2010·4 cites·10 claims
- 1177US6891231B2Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrierIBM·Filed 2001·Granted May 10, 2005·19 cites·18 claims
- 1272US9245759B2Method for manufacturing a dual work function semiconductor deviceIMEC·Filed 2013·Granted Jan 26, 2016·4 cites·20 claims
- 1369US11837652B2Semiconductor processing system with in-situ electrical bias and methods thereofTOKYO ELECTRON LTD·Filed 2022·Granted Dec 5, 2023·0 cites·20 claims
- 1468US10424517B2Method for manufacturing a dual work function semiconductor device and the semiconductor device made thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Sep 24, 2019·1 cites·20 claims
- 1562US9892923B2Method for tuning the effective work function of a metalIMEC VZW·Filed 2015·Granted Feb 13, 2018·1 cites·18 claims
- 1660US11335792B2Semiconductor processing system with in-situ electrical bias and methods thereofTOKYO ELECTRON LTD·Filed 2020·Granted May 17, 2022·0 cites·20 claims
- 1754US11894240B2Semiconductor processing systems with in-situ electrical biasTOKYO ELECTRON LTD·Filed 2021·Granted Feb 6, 2024·0 cites·23 claims
- 1849US7812413B2MOSFET devices and methods for making themIMEC·Filed 2008·Granted Oct 12, 2010·0 cites·19 claims
- 1944US2010219481A1Method for manufacturing a dual work function semiconductor device and the semiconductor device made thereofIMEC·Filed 2010·Application pending·0 cites
- 2042US8211812B2Method for fabricating a high-K dielectric layerRAGNARSSON LARS-AKE·Filed 2008·Granted Jul 3, 2012·0 cites·15 claims
- 2141US7488640B2Aluminum nitride and aluminum oxide/aluminum nitride heterostructure gate dielectric stack based field effect transistors and method for forming sameIBM·Filed 2004·Granted Feb 10, 2009·0 cites·8 claims
- 2240US2008308881A1Method for Controlled Formation of a Gate Dielectric StackIMEC INTER UNI MICRO ELECTR·Filed 2008·Application pending·0 cites
- 2340US2008254605A1Method of reducing the interfacial oxide thicknessIMEC INTER UNI MICRO ELECTR·Filed 2007·Application pending·0 cites
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