Inventor · disambiguated record
Lester Crudele
Also filed as: CRUDELE LESTER · CRUDELE LESTER M
35 granted patents·683 citations·filing 1980–2022
97Inventor score
Files withSPIN TRANSFER TECH INC15MOTOROLA INC6SPIN MEMORY INC6INTEGRATED SILICON SOLUTION CAYMAN INC4MIPS COMPUTER SYSTEMS INC3
Top patents by PatentIndex Score
35 records- 0193US4953073ACup chip having tag comparator and address translation unit on chip and connected to off-chip cache and main memoriesMIPS COMPUTER SYSTEMS INC·Filed 1986·Granted Aug 28, 1990·143 cites·2 claims
- 0288US4947357AScan testing a digital system using scan chains in integrated circuitsSTELLAR COMPUTER·Filed 1988·Granted Aug 7, 1990·94 cites·4 claims
- 0387US4805098AWrite bufferMIPS COMPUTER SYSTEMS INC·Filed 1986·Granted Feb 14, 1989·109 cites·9 claims
- 0485US10460781B2Memory device with a dual Y-multiplexer structure for performing two simultaneous operations on the same row of a memory bankSPIN TRANSFER TECH INC·Filed 2017·Granted Oct 29, 2019·6 cites·17 claims
- 0582US5113506ASystem having an address generating unit and a log comparator packaged as an integrated circuit seperate from cache log memory and cache data memoryMIPS COMPUTER SYSTEMS INC·Filed 1990·Granted May 12, 1992·81 cites·8 claims
- 0680US4633437AData processor having dynamic bus sizingMOTOROLA INC·Filed 1984·Granted Dec 30, 1986·60 cites·18 claims
- 0778US4710866AMethod and apparatus for validating prefetched instructionMOTOROLA INC·Filed 1986·Granted Dec 1, 1987·64 cites·2 claims
- 0876US4349873AMicroprocessor interrupt processingMOTOROLA INC·Filed 1980·Granted Sep 14, 1982·47 cites·4 claims
- 0973US10395711B2Perpendicular source and bit lines for an MRAM arraySPIN TRANSFER TECH INC·Filed 2017·Granted Aug 27, 2019·3 cites·11 claims
- 1067US11941299B2MRAM access coordination systems and methods via pipeline in parallelINTEGRATED SILICON SOLUTION CAYMAN INC·Filed 2022·Granted Mar 26, 2024·0 cites·7 claims
- 1167US10446210B2Memory instruction pipeline with a pre-read stage for a write operation for reducing power consumption in a memory device that uses dynamic redundancy registersSPIN TRANSFER TECH INC·Filed 2017·Granted Oct 15, 2019·2 cites·20 claims
- 1267US10437723B2Method of flushing the contents of a dynamic redundancy register to a secure storage area during a power down in a memory deviceSPIN TRANSFER TECH INC·Filed 2017·Granted Oct 8, 2019·2 cites·20 claims
- 1365US4488228AVirtual memory data processorMOTOROLA INC·Filed 1982·Granted Dec 11, 1984·29 cites·6 claims
- 1463US10366775B2Memory device using levels of dynamic redundancy registers for writing a data word that failed a write operationSPIN TRANSFER TECH INC·Filed 2017·Granted Jul 30, 2019·1 cites·24 claims
- 1562US11334288B2MRAM access coordination systems and methods with a plurality of pipelinesINTEGRATED SILICON SOLUTION CAYMAN INC·Filed 2019·Granted May 17, 2022·0 cites·16 claims
- 1661US10489245B2Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to short during testing and using on-the-fly bit failure detection and bit redundancy remapping techniques to correct themSPIN TRANSFER TECH INC·Filed 2017·Granted Nov 26, 2019·1 cites·20 claims
- 1760US10192602B2Smart cache design to prevent overflow for a memory device with a dynamic redundancy registerSPIN TRANSFER TECH INC·Filed 2017·Granted Jan 29, 2019·1 cites·23 claims
- 1859US10192601B2Memory instruction pipeline with an additional write stage in a memory device that uses dynamic redundancy registersSPIN TRANSFER TECH INC·Filed 2017·Granted Jan 29, 2019·1 cites·21 claims
- 1958US4348722ABus error recognition for microprogrammed data processorMOTOROLA INC·Filed 1980·Granted Sep 7, 1982·23 cites·4 claims
- 2055US11386010B2Circuit engine for managing memory meta-stabilityINTEGRATED SILICON SOLUTION CAYMAN INC·Filed 2020·Granted Jul 12, 2022·0 cites·20 claims
- 2153US11010294B2MRAM noise mitigation for write operations with simultaneous background operationsSPIN MEMORY INC·Filed 2019·Granted May 18, 2021·0 cites·20 claims
- 2252US10437491B2Method of processing incomplete memory operations in a memory device during a power up sequence and a power down sequence using a dynamic redundancy registerSPIN TRANSFER TECH INC·Filed 2017·Granted Oct 8, 2019·0 cites·20 claims
- 2351US10424393B2Method of reading data from a memory device using multiple levels of dynamic redundancy registersSPIN TRANSFER TECH INC·Filed 2017·Granted Sep 24, 2019·0 cites·25 claims
- 2448US11151042B2Error cache segmentation for power reductionINTEGRATED SILICON SOLUTION CAYMAN INC·Filed 2019·Granted Oct 19, 2021·0 cites·20 claims
- 2548US10366774B2Device with dynamic redundancy registersSPIN TRANSFER TECH INC·Filed 2016·Granted Jul 30, 2019·0 cites·24 claims
- 2648US4757445AMethod and apparatus for validating prefetched instructionMOTOROLA INC·Filed 1987·Granted Jul 12, 1988·16 cites·2 claims
- 2742US10990465B2MRAM noise mitigation for background operations by delaying verify timingSPIN MEMORY INC·Filed 2019·Granted Apr 27, 2021·0 cites·20 claims
- 2842US10529439B2On-the-fly bit failure detection and bit redundancy remapping techniques to correct for fixed bit defectsSPIN MEMORY INC·Filed 2017·Granted Jan 7, 2020·0 cites·32 claims
- 2940US10628316B2Memory device with a plurality of memory banks where each memory bank is associated with a corresponding memory instruction pipeline and a dynamic redundancy registerSPIN TRANSFER TECH INC·Filed 2017·Granted Apr 21, 2020·0 cites·17 claims
- 3040US10481976B2Forcing bits as bad to widen the window between the distributions of acceptable high and low resistive bits thereby lowering the margin and increasing the speed of the sense amplifiersSPIN TRANSFER TECH INC·Filed 2017·Granted Nov 19, 2019·0 cites·24 claims
- 3140US10395712B2Memory array with horizontal source line and sacrificial bitline per virtual sourceSPIN TRANSFER TECH INC·Filed 2017·Granted Aug 27, 2019·0 cites·20 claims
- 3239US10656994B2Over-voltage write operation of tunnel magnet-resistance (“TMR”) memory device and correcting failure bits therefrom by using on-the-fly bit failure detection and bit redundancy remapping techniquesSPIN MEMORY INC·Filed 2017·Granted May 19, 2020·0 cites·19 claims
- 3338US10360964B2Method of writing contents in memory during a power up sequence using a dynamic redundancy register in a memory deviceSPIN TRANSFER TECH INC·Filed 2017·Granted Jul 23, 2019·0 cites·20 claims
- 3437US10891997B2Memory array with horizontal source line and a virtual source lineSPIN MEMORY INC·Filed 2017·Granted Jan 12, 2021·0 cites·19 claims
- 3536US10546624B2Multi-port random access memorySPIN MEMORY INC·Filed 2017·Granted Jan 28, 2020·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →