Inventor · disambiguated record
Leonard P. Guler
Also filed as: GULER LEONARD · GULER LEONARD P
78 granted patents·156 pending applications·68 citations·filing 2013–2025
98Inventor score
Top patents by PatentIndex Score
234 records- 0198US11855223B2Self-aligned gate endcap (SAGE) architectures with gate-all-around devicesINTEL CORP·Filed 2021·Granted Dec 26, 2023·6 cites·20 claims
- 0296US12342612B2Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regionsINTEL CORP·Filed 2023·Granted Jun 24, 2025·2 cites·20 claims
- 0396US12266708B2Integrated circuit structures having dielectric anchor voidINTEL CORP·Filed 2023·Granted Apr 1, 2025·2 cites·25 claims
- 0496US11862635B2Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regionsINTEL CORP·Filed 2022·Granted Jan 2, 2024·2 cites·20 claims
- 0595US11929396B2Cavity spacer for nanowire transistorsINTEL CORP·Filed 2022·Granted Mar 12, 2024·2 cites·20 claims
- 0694US11233152B2Self-aligned gate endcap (SAGE) architectures with gate-all-around devicesINTEL CORP·Filed 2018·Granted Jan 25, 2022·6 cites·23 claims
- 0793US11342411B2Cavity spacer for nanowire transistorsINTEL CORP·Filed 2018·Granted May 24, 2022·7 cites·18 claims
- 0890US12002810B2Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approachINTEL CORP·Filed 2018·Granted Jun 4, 2024·5 cites·13 claims
- 0990US10559529B2Pitch division patterning approaches with increased overlay margin for back end of line (BEOL) interconnect fabrication and structures resulting therefromINTEL CORP·Filed 2016·Granted Feb 11, 2020·6 cites·26 claims
- 1089US11398474B2Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regionsINTEL CORP·Filed 2018·Granted Jul 26, 2022·4 cites·12 claims
- 1188US12382706B2Self-aligned gate endcap (SAGE) architectures with gate-all-around devicesINTEL CORP·Filed 2024·Granted Aug 5, 2025·0 cites·23 claims
- 1288US12364002B2Integrated circuit structures having metal gates with tapered plugsINTEL CORP·Filed 2021·Granted Jul 15, 2025·2 cites·20 claims
- 1388US2025126832A1Self-aligned gate endcap (sage) architectures with gate-all-around devicesINTEL CORP·Filed 2024·Application pending·0 cites
- 1486US12224350B2Self-aligned gate endcap (SAGE) architectures with gate-all-around devicesINTEL CORP·Filed 2023·Granted Feb 11, 2025·0 cites·20 claims
- 1586US11404578B2Dielectric isolation layer between a nanowire transistor and a substrateINTEL CORP·Filed 2018·Granted Aug 2, 2022·3 cites·18 claims
- 1686US10541143B2Self-aligned build-up of topographic featuresINTEL CORP·Filed 2016·Granted Jan 21, 2020·4 cites·20 claims
- 1785US11302790B2Fin shaping using templates and integrated circuit structures resulting therefromINTEL CORP·Filed 2018·Granted Apr 12, 2022·3 cites·22 claims
- 1884US11043492B2Self-aligned gate edge trigate and finFET devicesINTEL CORP·Filed 2016·Granted Jun 22, 2021·4 cites·16 claims
- 1983US12328905B2Cavity spacer for nanowire transistorsINTEL CORP·Filed 2024·Granted Jun 10, 2025·0 cites·20 claims
- 2083US12211925B2Gate-all-around integrated circuit structures having oxide sub-finsINTEL CORP·Filed 2023·Granted Jan 28, 2025·0 cites·17 claims
- 2183US2025331300A1Integrated circuit structures having cut metal gatesINTEL CORP·Filed 2025·Application pending·0 cites
- 2282US2025280567A1Cavity spacer for nanowire transistorsINTEL CORP·Filed 2025·Application pending·0 cites
- 2381US11569231B2Non-planar transistors with channel regions having varying widthsINTEL CORP·Filed 2019·Granted Jan 31, 2023·3 cites·21 claims
- 2481US2025133821A1Integrated circuit structures having cut metal gatesINTEL CORP·Filed 2024·Application pending·0 cites
- 2581US2025120152A1Gate-all-around integrated circuit structures having oxide sub-finsINTEL CORP·Filed 2024·Application pending·0 cites
- 2680US12349394B2Dielectric isolation layer between a nanowire transistor and a substrateINTEL CORP·Filed 2024·Granted Jul 1, 2025·0 cites·21 claims
- 2779US11189614B2Process etch with reduced loading effectINTEL CORP·Filed 2018·Granted Nov 30, 2021·2 cites·15 claims
- 2879US10522402B2Grid self-aligned metal via processing schemes for back end of line (BEOL) interconnects and structures resulting therefromINTEL CORP·Filed 2015·Granted Dec 31, 2019·3 cites·25 claims
- 2979US2024347539A1Integrated circuit structures having cut metal gatesINTEL CORP·Filed 2024·Application pending·0 cites
- 3079US2025351561A1Integrated circuit structures with backside gate cut or trench contact cutINTEL CORP·Filed 2025·Application pending·0 cites
- 3177US12457771B2Plug and recess process for dual metal gate on stacked nanoribbon devicesINTEL CORP·Filed 2024·Granted Oct 28, 2025·0 cites·26 claims
- 3277US12426316B2Method of fabricating integrated circuits with fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric materialINTEL CORP·Filed 2022·Granted Sep 23, 2025·0 cites·24 claims
- 3376US2025029915A1Vertical metal splitting using helmets and wrap-around dielectric spacersINTEL CORP·Filed 2024·Application pending·0 cites
- 3475US12369392B2Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gatesINTEL CORP·Filed 2024·Granted Jul 22, 2025·0 cites·20 claims
- 3574US12369393B2Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approachINTEL CORP·Filed 2024·Granted Jul 22, 2025·0 cites·20 claims
- 3673US12501659B2Integrated circuit structures having dielectric anchor voidINTEL CORP·Filed 2021·Granted Dec 16, 2025·0 cites·20 claims
- 3773US12249541B2Vertical edge blocking (VEB) technique for increasing patterning process marginINTEL CORP·Filed 2023·Granted Mar 11, 2025·0 cites·7 claims
- 3873US12080639B2Contact over active gate structures with metal oxide layers to inhibit shortingINTEL CORP·Filed 2019·Granted Sep 3, 2024·1 cites·17 claims
- 3973US11901458B2Dielectric isolation layer between a nanowire transistor and a substrateINTEL CORP·Filed 2022·Granted Feb 13, 2024·0 cites·22 claims
- 4073US2024355903A1Self-aligned gate endcap (sage) architectures with gate-all-around devices above insulator substratesINTEL CORP·Filed 2024·Application pending·0 cites
- 4173US2025254923A1Gate-all-around integrated circuit structures having depopulated channel structures using backside removal approachINTEL CORP·Filed 2025·Application pending·0 cites
- 4272US12014959B2Integrated nanowire and nanoribbon patterning in transistor manufactureINTEL CORP·Filed 2021·Granted Jun 18, 2024·0 cites·20 claims
- 4372US11972979B21D vertical edge blocking (VEB) via and plugINTEL CORP·Filed 2023·Granted Apr 30, 2024·0 cites·22 claims
- 4472US2025227991A1Integrated circuit structures with backside gate partial cut or trench contact partial cutINTEL CORP·Filed 2025·Application pending·0 cites
- 4570US11749733B2FIN shaping using templates and integrated circuit structures resulting therefromINTEL CORP·Filed 2022·Granted Sep 5, 2023·0 cites·22 claims
- 4670US2025204032A1Selective growth self-aligned gate endcap (sage) architectures without fin end gapINTEL CORP·Filed 2025·Application pending·0 cites
- 4770US2024154037A1Integrated circuit structures having dielectric anchor and confined epitaxial source or drain structureINTEL CORP·Filed 2023·Application pending·0 cites
- 4869US12501684B2Integrated circuit structures with backside self-aligned penetrating conductive source or drain contactINTEL CORP·Filed 2022·Granted Dec 16, 2025·0 cites·20 claims
- 4969US2022392898A1Integrated circuit structures having cut metal gatesINTEL CORP·Filed 2021·Application pending·0 cites
- 5069US2022399451A1Gate-all-around integrated circuit structures having depopulated channel structures using backside removal approachINTEL CORP·Filed 2021·Application pending·0 cites
Showing the top 50 of 234 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →