Inventor · disambiguated record
Linus Jang
Also filed as: JANG LINUS
19 granted patents·3 pending applications·102 citations·filing 2008–2018
92Inventor score
Top patents by PatentIndex Score
22 records- 0196US9209038B2Methods for fabricating integrated circuits using self-aligned quadruple patterningGLOBALFOUNDRIES INC·Filed 2014·Granted Dec 8, 2015·34 cites·20 claims
- 0294US7940457B2Energy-efficient optoelectronic smart windowUNIV ILLINOIS·Filed 2008·Granted May 10, 2011·30 cites·80 claims
- 0389US9595478B2Dummy gate used as interconnection and method of making the sameGLOBALFOUNDRIES INC·Filed 2015·Granted Mar 14, 2017·6 cites·12 claims
- 0486US9214360B2Methods of patterning features having differing widthsGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 15, 2015·6 cites·17 claims
- 0586US9184263B2Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devicesGLOBALFOUNDRIES INC·Filed 2013·Granted Nov 10, 2015·7 cites·20 claims
- 0681US10297510B1Sidewall image transfer process for multiple gate width patterningIBM·Filed 2018·Granted May 21, 2019·3 cites·14 claims
- 0781US9209037B2Methods for fabricating integrated circuits including selectively forming and removing fin structuresGLOBALFOUNDRIES INC·Filed 2014·Granted Dec 8, 2015·5 cites·19 claims
- 0876US9449835B2Methods of forming features having differing pitch spacing and critical dimensionsGLOBALFOUNDRIES INC·Filed 2015·Granted Sep 20, 2016·2 cites·18 claims
- 0975US10181420B2Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less viasGLOBALFOUNDRIES INC·Filed 2017·Granted Jan 15, 2019·2 cites·10 claims
- 1075US9653571B2Freestanding spacer having sub-lithographic lateral dimension and method of forming sameIBM·Filed 2015·Granted May 16, 2017·2 cites·20 claims
- 1172US9045933B2Energy-efficient smart window systemJAIN KANTI·Filed 2011·Granted Jun 2, 2015·3 cites·20 claims
- 1263US9431264B2Methods of forming integrated circuits and multiple critical dimension self-aligned double patterning processesGLOBALFOUNDRIES INC·Filed 2013·Granted Aug 30, 2016·1 cites·19 claims
- 1360US8716094B1FinFET formation using double patterning memorizationGLOBALFOUNDRIES INC·Filed 2012·Granted May 6, 2014·1 cites·17 claims
- 1455US2015214331A1Replacement metal gate including dielectric gate materialIBM·Filed 2014·Application pending·0 cites
- 1554US9842741B2Removal of semiconductor growth defectsIBM·Filed 2016·Granted Dec 12, 2017·0 cites·10 claims
- 1654US9496257B2Removal of semiconductor growth defectsIBM·Filed 2014·Granted Nov 15, 2016·0 cites·8 claims
- 1753US9653573B2Replacement metal gate including dielectric gate materialIBM·Filed 2015·Granted May 16, 2017·0 cites·1 claims
- 1851US10283505B2Dummy gate used as interconnection and method of making the sameGLOBALFOUNDRIES INC·Filed 2017·Granted May 7, 2019·0 cites·13 claims
- 1951US9466505B2Methods of patterning features having differing widthsGLOBALFOUNDRIES INC·Filed 2015·Granted Oct 11, 2016·0 cites·18 claims
- 2051US2016172467A1Replacement metal gate including dielectric gate materialIBM·Filed 2016·Application pending·0 cites
- 2146US8871649B2Methods of forming trench/hole type features in a layer of material of an integrated circuit productGLOBAL FOUNDRIES INC·Filed 2013·Granted Oct 28, 2014·0 cites·20 claims
- 2227US2016336172A1Lithography stack and methodGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →