Inventor · disambiguated record
Mayukh Bhattacharya
Also filed as: BHATTACHARYA MAYUKH
16 granted patents·6 pending applications·59 citations·filing 2000–2025
89Inventor score
Top patents by PatentIndex Score
22 records- 0190US11579994B2Fast and scalable methodology for analog defect detectability analysisSYNOPSYS INC·Filed 2021·Granted Feb 14, 2023·3 cites·20 claims
- 0288US11620424B2Transistor—level defect coverage and defect simulationSYNOPSYS INC·Filed 2021·Granted Apr 4, 2023·3 cites·20 claims
- 0388US6323709B1High-speed, compact, edge-triggered, flip-flop circuitUNIV MICHIGAN·Filed 2000·Granted Nov 27, 2001·43 cites·33 claims
- 0483US12332301B2Measuring device defect sensitization in transistor-level circuitsSYNOPSYS INC·Filed 2022·Granted Jun 17, 2025·1 cites·8 claims
- 0583US11734482B1Visual representation to assess quality of input stimulus in transistor-level circuitsSYNOPSYS INC·Filed 2021·Granted Aug 22, 2023·2 cites·20 claims
- 0671US12271668B1Finding equivalent classes of hard defects in stacked MOSFET arraysSYNOPSYS INC·Filed 2023·Granted Apr 8, 2025·0 cites·20 claims
- 0770US2025290974A1Measuring device defect sensitization in transistor-level circuitsSYNOPSYS INC·Filed 2025·Application pending·0 cites
- 0861US12481813B2Test point insertion in analog circuit design testingSYNOPSYS INC·Filed 2023·Granted Nov 25, 2025·0 cites·20 claims
- 0961US11797737B2Finding equivalent classes of hard defects in stacked MOSFET arraysSYNOPSYS INC·Filed 2021·Granted Oct 24, 2023·0 cites·20 claims
- 1061US2025238584A1Prediction-based termination of analog circuit simulationsSYNOPSYS INC·Filed 2024·Application pending·0 cites
- 1159US8060355B2Automatic, hierarchy-independent partitioning method for transistor-level circuit simulationKERNS KEVIN J·Filed 2007·Granted Nov 15, 2011·5 cites·7 claims
- 1257US11669667B2Automatic test pattern generation (ATPG) for parametric faultsSYNOPSYS INC·Filed 2021·Granted Jun 6, 2023·0 cites·18 claims
- 1356US9032352B2Method of optimizing capacitive couplings in high-capacitance nets in simulation of post-layout circuitsSYNOPSYS INC·Filed 2013·Granted May 12, 2015·1 cites·24 claims
- 1456US2025258220A1Detection of malicious circuits inserted in analog circuitsSYNOPSYS INC·Filed 2024·Application pending·0 cites
- 1554US10409941B2Visual representation of circuit related dataSYNOPSYS INC·Filed 2013·Granted Sep 10, 2019·1 cites·19 claims
- 1652US11141777B2Multi-piece jaw assembly for surgical clip applierETHICON LLC·Filed 2018·Granted Oct 12, 2021·0 cites·18 claims
- 1751US2024193336A1Automatic test pattern generation to increase coverage in detecting defects in analog circuitsSYNOPSYS INC·Filed 2022·Application pending·0 cites
- 1846US11361135B2Guiding sample size choice in analog defect or fault simulationSYNOPSYS INC·Filed 2021·Granted Jun 14, 2022·0 cites·20 claims
- 1943US11443092B2Defect weight formulas for analog defect simulationSYNOPSYS INC·Filed 2020·Granted Sep 13, 2022·0 cites·20 claims
- 2040US2021312113A1Method for finding equivalent classes of hard defects in stacked mosfet arraysSYNOPSYS INC·Filed 2021·Application pending·0 cites
- 2138US2016379175A1System and Method for Automated Optimized Personal Task Scheduling and Targeted AdvertisingBHATTACHARYA MAYUKH·Filed 2015·Application pending·0 cites
- 2235US11763056B2Method and system for custom model definition of analog defects in an integrated circuitSYNOPSYS INC·Filed 2021·Granted Sep 19, 2023·0 cites·13 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →