Inventor · disambiguated record
Mark Bluhm
Also filed as: BLUHM MARK · BLUHM MARK W
36 granted patents·1,325 citations·filing 1986–2007
98Inventor score
Top patents by PatentIndex Score
36 records- 0190US6343363B1Method of invoking a low power mode in a computer system using a halt instructionNAT SEMICONDUCTOR CORP·Filed 2000·Granted Jan 29, 2002·40 cites·10 claims
- 0285US5630149APipelined processor with register renaming hardware to accommodate multiple size registersCYRIX CORP·Filed 1995·Granted May 13, 1997·125 cites·16 claims
- 0382US5963984AAddress translation unit employing programmable page sizeNAT SEMICONDUCTOR CORP·Filed 1997·Granted Oct 5, 1999·100 cites·15 claims
- 0482US5907860ASystem and method of retiring store data from a write bufferNAT SEMICONDUCTOR CORP·Filed 1996·Granted May 25, 1999·90 cites·3 claims
- 0582US5630143AMicroprocessor with externally controllable power managementCYRIX CORP·Filed 1994·Granted May 13, 1997·81 cites·14 claims
- 0679US6138230AProcessor with multiple execution pipelines using pipe stage state information to control independent movement of instructions between pipe stages of an execution pipelineVIA CYRIX INC·Filed 1997·Granted Oct 24, 2000·88 cites·12 claims
- 0778US5524234ACoherency for write-back cache in a system designed for write-through cache including write-back latency controlCYRIX CORP·Filed 1994·Granted Jun 4, 1996·60 cites·13 claims
- 0877US5584009ASystem and method of retiring store data from a write bufferCYRIX CORP·Filed 1993·Granted Dec 10, 1996·62 cites·16 claims
- 0977US5479616AException handling for prefetched instruction bytes using valid bits to identify instructions that will cause an exceptionCYRIX CORP·Filed 1992·Granted Dec 26, 1995·74 cites·11 claims
- 1074US6205560B1Debug system allowing programmable selection of alternate debug mechanisms such as debug handler, SMI, or JTAGVIA CYRIX INC·Filed 1996·Granted Mar 20, 2001·76 cites·22 claims
- 1174US5632037AMicroprocessor having power management circuitry with coprocessor supportCYRIX CORP·Filed 1992·Granted May 20, 1997·64 cites·8 claims
- 1273US7120810B2Instruction-initiated power management method for a pipelined data processorNAT SEMICONDUCTOR CORP·Filed 2004·Granted Oct 10, 2006·10 cites·82 claims
- 1372US6910141B2Pipelined data processor with signal-initiated power management controlNAT SEMICONDUCTOR CORP·Filed 2004·Granted Jun 21, 2005·9 cites·130 claims
- 1471US6088807AComputer system with low power mode invoked by halt instructionNAT SEMICONDUCTOR CORP·Filed 1996·Granted Jul 11, 2000·54 cites·9 claims
- 1570US7900076B2Power management method for a pipelined computer systemNAT SEMICONDUCTOR CORP·Filed 2007·Granted Mar 1, 2011·2 cites·12 claims
- 1670US7062666B2Signal-initiated method for suspending operation of a pipelined data processorNAT SEMICONDUCTOR CORP·Filed 2004·Granted Jun 13, 2006·8 cites·41 claims
- 1769US5860111ACoherency for write-back cache in a system designed for write-through cache including export-on-holdNAT SEMICONDUCTOR CORP·Filed 1995·Granted Jan 12, 1999·45 cites·14 claims
- 1868US6721894B2Method for controlling power of a microprocessor by asserting and de-asserting a control signal in response conditions associated with the microprocessor entering and exiting low power state respectivelyNAT SEMICONDUCTOR CORP·Filed 2002·Granted Apr 13, 2004·8 cites·42 claims
- 1967US7000132B2Signal-initiated power management method for a pipelined data processorNAT SEMICONDUCTOR CORP·Filed 2004·Granted Feb 14, 2006·6 cites·124 claims
- 2063US6073231APipelined processor with microcontrol of register translation hardwareVIA CYRIX INC·Filed 1997·Granted Jun 6, 2000·43 cites·7 claims
- 2163US5664149ACoherency for write-back cache in a system designed for write-through cache using an export/invalidate protocolCYRIX CORP·Filed 1993·Granted Sep 2, 1997·30 cites·6 claims
- 2262US5937178ARegister file for registers with multiple addressable sizes using read-modify-write for register file updateNAT SEMICONDUCTOR CORP·Filed 1997·Granted Aug 10, 1999·41 cites·6 claims
- 2362US5838897ADebugging a processor using data output during idle bus cyclesCYRIX CORP·Filed 1996·Granted Nov 17, 1998·40 cites·18 claims
- 2457US6694443B1System for controlling power of a microprocessor by asserting and de-asserting a control signal in response to condition associated with the microprocessor entering and exiting low power state respectivelyNAT SEMICONDUCTOR CORP·Filed 2001·Granted Feb 17, 2004·4 cites·84 claims
- 2557US4729093AMicrocomputer which prioritizes instruction prefetch requests and data operand requestsMOTOROLA INC·Filed 1987·Granted Mar 1, 1988·24 cites·2 claims
- 2655US7900075B2Pipelined computer system with power management controlNAT SEMICONDUCTOR CORP·Filed 2007·Granted Mar 1, 2011·0 cites·14 claims
- 2754US5784589ADistributed free register tracking for register renaming using an availability tracking register associated with each stage of an execution pipelineCYRIX CORP·Filed 1996·Granted Jul 21, 1998·29 cites·20 claims
- 2851US6978390B2Pipelined data processor with instruction-initiated power management controlNAT SEMICONDUCTOR CORP·Filed 2004·Granted Dec 20, 2005·2 cites·88 claims
- 2951US5771365ACondensed microaddress generation in a complex instruction set computerCYRIX CORP·Filed 1995·Granted Jun 23, 1998·24 cites·8 claims
- 3050US5159210ALine precharging circuits and methodsCYRIX CORP·Filed 1991·Granted Oct 27, 1992·13 cites·30 claims
- 3149US4763253AMicrocomputer with change of flowMOTOROLA INC·Filed 1986·Granted Aug 9, 1988·16 cites·7 claims
- 3244US7509512B2Instruction-initiated method for suspending operation of a pipelined data processorNAT SEMICONDUCTOR CORP·Filed 2004·Granted Mar 24, 2009·0 cites·24 claims
- 3344US5898815AI/O bus interface recovery counter dependent upon minimum bus clocks to prevent overrun and ratio of execution core clock frequency to system bus clock frequencyNAT SEMICONDUCTOR CORP·Filed 1996·Granted Apr 27, 1999·17 cites·15 claims
- 3444US5596731ASingle clock bus transfers during burst and non-burst cyclesCYRIX CORP·Filed 1995·Granted Jan 21, 1997·18 cites·18 claims
- 3540US5375209AMicroprocessor for selectively configuring pinout by activating tri-state device to disable internal clock from external pinCYRIX CORP·Filed 1992·Granted Dec 20, 1994·12 cites·8 claims
- 3639US5644741AProcessor with single clock decode architecture employing single microROMCYRIX CORP·Filed 1993·Granted Jul 1, 1997·10 cites·13 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →