Inventor · disambiguated record
Manoj Dusanapudi
Also filed as: DUSANAPUDI MANOJ
68 granted patents·4 pending applications·278 citations·filing 2007–2023
98Inventor score
Top patents by PatentIndex Score
72 records- 0196US9612929B1Efficient validation/verification of coherency and snoop filtering mechanisms in computing systemsIBM·Filed 2016·Granted Apr 4, 2017·16 cites·15 claims
- 0296US9594680B1Identifying stale entries in address translation cacheIBM·Filed 2016·Granted Mar 14, 2017·16 cites·1 claims
- 0392US9542290B1Replicating test case data into a cache with non-naturally aligned data boundariesIBM·Filed 2016·Granted Jan 10, 2017·7 cites·3 claims
- 0491US9910941B2Test case generationIBM·Filed 2016·Granted Mar 6, 2018·11 cites·1 claims
- 0591US9514036B1Test case generationIBM·Filed 2016·Granted Dec 6, 2016·11 cites·1 claims
- 0690US10169186B1Efficient testing of direct memory address translationIBM·Filed 2017·Granted Jan 1, 2019·5 cites·15 claims
- 0790US7752499B2System and method for using resource pools and instruction pools for processor design verification and validationIBM·Filed 2007·Granted Jul 6, 2010·25 cites·20 claims
- 0890US7647539B2System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validationIBM·Filed 2007·Granted Jan 12, 2010·29 cites·18 claims
- 0988US10169185B1Efficient testing of direct memory address translationIBM·Filed 2017·Granted Jan 1, 2019·4 cites·11 claims
- 1086US7669083B2System and method for re-shuffling test case instruction orders for processor design verification and validationIBM·Filed 2007·Granted Feb 23, 2010·22 cites·20 claims
- 1184US7992059B2System and method for testing a large memory area during processor design verification and validationIBM·Filed 2007·Granted Aug 2, 2011·15 cites·20 claims
- 1283US8832502B2Hardware verification using acceleration platformDUSANAPUDI MANOJ·Filed 2012·Granted Sep 9, 2014·11 cites·16 claims
- 1383US7747908B2System and method for creating different start cache and bus states using multiple test patterns for processor design verification and validationIBM·Filed 2007·Granted Jun 29, 2010·14 cites·20 claims
- 1482US7797650B2System and method for testing SLB and TLB cells during processor design verification and validationIBM·Filed 2007·Granted Sep 14, 2010·14 cites·20 claims
- 1578US7661023B2System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validationIBM·Filed 2007·Granted Feb 9, 2010·9 cites·20 claims
- 1677US10169180B2Replicating test code and test data into a cache with non-naturally aligned data boundariesIBM·Filed 2016·Granted Jan 1, 2019·2 cites·19 claims
- 1777US9921897B2Testing a non-core MMUIBM·Filed 2016·Granted Mar 20, 2018·2 cites·10 claims
- 1876US9940226B2Synchronization of hardware agents in a computer systemIBM·Filed 2016·Granted Apr 10, 2018·2 cites·15 claims
- 1976US9501408B2Efficient validation of coherency between processor cores and accelerators in computer systemsGLOBALFOUNDRIES INC·Filed 2013·Granted Nov 22, 2016·4 cites·13 claims
- 2075US9286133B2Verification of dynamic logical partitioningGLOBALFOUNDRIES INC·Filed 2013·Granted Mar 15, 2016·3 cites·7 claims
- 2174US12130749B2Validation of store coherence relative to page translation invalidationIBM·Filed 2023·Granted Oct 29, 2024·0 cites·20 claims
- 2274US9697138B2Identifying stale entries in address translation cacheIBM·Filed 2017·Granted Jul 4, 2017·1 cites·1 claims
- 2374US9594672B1Test case generationIBM·Filed 2016·Granted Mar 14, 2017·2 cites·1 claims
- 2474US9298516B2Verification of dynamic logical partitioningGLOBALFOUNDRIES INC·Filed 2013·Granted Mar 29, 2016·3 cites·13 claims
- 2574US7739570B2System and method for increasing error checking performance by calculating CRC calculations after multiple test patterns for processor design verification and validationIBM·Filed 2007·Granted Jun 15, 2010·7 cites·20 claims
- 2674US7584394B2System and method for pseudo-random test pattern memory allocation for processor design verification and validationIBM·Filed 2007·Granted Sep 1, 2009·7 cites·20 claims
- 2773US10521355B2Method, system, and apparatus for stress testing memory translation tablesIBM·Filed 2017·Granted Dec 31, 2019·1 cites·20 claims
- 2873US8099559B2System and method for generating fast instruction and data interrupts for processor design verification and validationCHOUDHURY SHUBHODEEP ROY·Filed 2007·Granted Jan 17, 2012·9 cites·20 claims
- 2972US11163661B2Test case generation for a hardware state spaceIBM·Filed 2019·Granted Nov 2, 2021·1 cites·20 claims
- 3072US7966521B2Light weight and high throughput test case generation methodology for testing cache/TLB intervention and diagnosticsIBM·Filed 2008·Granted Jun 21, 2011·5 cites·20 claims
- 3170US10223225B2Testing speculative instruction execution with test cases placed in memory segments with non-naturally aligned data boundariesIBM·Filed 2016·Granted Mar 5, 2019·1 cites·20 claims
- 3268US9043569B2Memory data managementIBM·Filed 2013·Granted May 26, 2015·3 cites·20 claims
- 3368US7689886B2System and method for predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification and validationIBM·Filed 2007·Granted Mar 30, 2010·7 cites·20 claims
- 3467US11620235B1Validation of store coherence relative to page translation invalidationIBM·Filed 2021·Granted Apr 4, 2023·0 cites·20 claims
- 3564US10318667B2Test case generationIBM·Filed 2015·Granted Jun 11, 2019·1 cites·14 claims
- 3663US11061821B2Method, system, and apparatus for stress testing memory translation tablesIBM·Filed 2019·Granted Jul 13, 2021·0 cites·20 claims
- 3763US10489261B2Efficient testing of direct memory address translationIBM·Filed 2018·Granted Nov 26, 2019·0 cites·16 claims
- 3863US10481991B2Efficient testing of direct memory address translationIBM·Filed 2018·Granted Nov 19, 2019·0 cites·19 claims
- 3962US10713179B2Efficiently generating effective address translations for memory management test casesIBM·Filed 2019·Granted Jul 14, 2020·0 cites·20 claims
- 4062US10489259B2Replicating test case data into a cache with non-naturally aligned data boundariesIBM·Filed 2018·Granted Nov 26, 2019·0 cites·10 claims
- 4162US10261917B2Identifying stale entries in address translation cacheIBM·Filed 2017·Granted Apr 16, 2019·0 cites·14 claims
- 4261US12450411B2Hazard generating for speculative cores in a microprocessorIBM·Filed 2021·Granted Oct 21, 2025·0 cites·20 claims
- 4361US8127192B2Predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification/validation in interrupt modeARORA SAMPAN·Filed 2008·Granted Feb 28, 2012·4 cites·20 claims
- 4459US9720845B2Identifying stale entries in address translation cacheIBM·Filed 2017·Granted Aug 1, 2017·0 cites·1 claims
- 4558US10540249B2Stress testing a processor memory with a link stackIBM·Filed 2017·Granted Jan 21, 2020·0 cites·15 claims
- 4658US9959182B2Replicating test case data into a cache with non-naturally aligned data boundariesIBM·Filed 2016·Granted May 1, 2018·0 cites·6 claims
- 4758US8019566B2System and method for efficiently testing cache congruence classes during processor design verification and validationIBM·Filed 2007·Granted Sep 13, 2011·1 cites·20 claims
- 4858US8006221B2System and method for testing multiple processor modes for processor design verification and validationIBM·Filed 2007·Granted Aug 23, 2011·2 cites·20 claims
- 4957US10261878B2Stress testing a processor memory with a link stackIBM·Filed 2017·Granted Apr 16, 2019·0 cites·12 claims
- 5057US9892060B2Identifying stale entries in address translation cacheIBM·Filed 2015·Granted Feb 13, 2018·0 cites·20 claims
Showing the top 50 of 72 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →