Inventor · disambiguated record
Margaret R. Herubin
Also filed as: HERUBIN MARGARET R
18 granted patents·435 citations·filing 1992–2007
96Inventor score
Top patents by PatentIndex Score
18 records- 0190US6343363B1Method of invoking a low power mode in a computer system using a halt instructionNAT SEMICONDUCTOR CORP·Filed 2000·Granted Jan 29, 2002·40 cites·10 claims
- 0282US5630143AMicroprocessor with externally controllable power managementCYRIX CORP·Filed 1994·Granted May 13, 1997·81 cites·14 claims
- 0378US5524234ACoherency for write-back cache in a system designed for write-through cache including write-back latency controlCYRIX CORP·Filed 1994·Granted Jun 4, 1996·60 cites·13 claims
- 0474US5632037AMicroprocessor having power management circuitry with coprocessor supportCYRIX CORP·Filed 1992·Granted May 20, 1997·64 cites·8 claims
- 0573US7120810B2Instruction-initiated power management method for a pipelined data processorNAT SEMICONDUCTOR CORP·Filed 2004·Granted Oct 10, 2006·10 cites·82 claims
- 0672US6910141B2Pipelined data processor with signal-initiated power management controlNAT SEMICONDUCTOR CORP·Filed 2004·Granted Jun 21, 2005·9 cites·130 claims
- 0771US6088807AComputer system with low power mode invoked by halt instructionNAT SEMICONDUCTOR CORP·Filed 1996·Granted Jul 11, 2000·54 cites·9 claims
- 0870US7900076B2Power management method for a pipelined computer systemNAT SEMICONDUCTOR CORP·Filed 2007·Granted Mar 1, 2011·2 cites·12 claims
- 0970US7062666B2Signal-initiated method for suspending operation of a pipelined data processorNAT SEMICONDUCTOR CORP·Filed 2004·Granted Jun 13, 2006·8 cites·41 claims
- 1069US5860111ACoherency for write-back cache in a system designed for write-through cache including export-on-holdNAT SEMICONDUCTOR CORP·Filed 1995·Granted Jan 12, 1999·45 cites·14 claims
- 1168US6721894B2Method for controlling power of a microprocessor by asserting and de-asserting a control signal in response conditions associated with the microprocessor entering and exiting low power state respectivelyNAT SEMICONDUCTOR CORP·Filed 2002·Granted Apr 13, 2004·8 cites·42 claims
- 1267US7000132B2Signal-initiated power management method for a pipelined data processorNAT SEMICONDUCTOR CORP·Filed 2004·Granted Feb 14, 2006·6 cites·124 claims
- 1363US5664149ACoherency for write-back cache in a system designed for write-through cache using an export/invalidate protocolCYRIX CORP·Filed 1993·Granted Sep 2, 1997·30 cites·6 claims
- 1457US6694443B1System for controlling power of a microprocessor by asserting and de-asserting a control signal in response to condition associated with the microprocessor entering and exiting low power state respectivelyNAT SEMICONDUCTOR CORP·Filed 2001·Granted Feb 17, 2004·4 cites·84 claims
- 1555US7900075B2Pipelined computer system with power management controlNAT SEMICONDUCTOR CORP·Filed 2007·Granted Mar 1, 2011·0 cites·14 claims
- 1651US6978390B2Pipelined data processor with instruction-initiated power management controlNAT SEMICONDUCTOR CORP·Filed 2004·Granted Dec 20, 2005·2 cites·88 claims
- 1744US7509512B2Instruction-initiated method for suspending operation of a pipelined data processorNAT SEMICONDUCTOR CORP·Filed 2004·Granted Mar 24, 2009·0 cites·24 claims
- 1840US5375209AMicroprocessor for selectively configuring pinout by activating tri-state device to disable internal clock from external pinCYRIX CORP·Filed 1992·Granted Dec 20, 1994·12 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →