Inventor · disambiguated record
Mark J. Hickey
Also filed as: HICKEY MARK J · HICKEY MARK JOSEPH
26 granted patents·6 pending applications·217 citations·filing 1996–2016
96Inventor score
Top patents by PatentIndex Score
32 records- 0193US7873816B2Pre-loading context states by inactive hardware thread in advance of context switchIBM·Filed 2008·Granted Jan 18, 2011·36 cites·21 claims
- 0287US10042417B2Branch prediction with power usage prediction and controlIBM·Filed 2016·Granted Aug 7, 2018·4 cites·19 claims
- 0386US10067556B2Branch prediction with power usage prediction and controlIBM·Filed 2015·Granted Sep 4, 2018·4 cites·19 claims
- 0486US8930432B2Floating point execution unit with fixed point functionalityHICKEY MARK J·Filed 2011·Granted Jan 6, 2015·10 cites·22 claims
- 0586US8412980B2Fault tolerant stability critical execution checking using redundant execution pipelinesHICKEY MARK J·Filed 2010·Granted Apr 2, 2013·9 cites·19 claims
- 0685US8707094B2Fault tolerant stability critical execution checking using redundant execution pipelinesIBM·Filed 2013·Granted Apr 22, 2014·7 cites·20 claims
- 0783US7065101B2Modification of bus protocol packet for serial data synchronizationIBM·Filed 2001·Granted Jun 20, 2006·42 cites·11 claims
- 0881US9223753B2Dynamic range adjusting floating point execution unitIBM·Filed 2013·Granted Dec 29, 2015·5 cites·21 claims
- 0980US8412760B2Dynamic range adjusting floating point execution unitHICKEY MARK J·Filed 2008·Granted Apr 2, 2013·9 cites·18 claims
- 1077US8880852B2Detecting logically non-significant operation based on opcode and operand and setting flag to decode address specified in subsequent instruction as different addressHICKEY MARK J·Filed 2011·Granted Nov 4, 2014·4 cites·25 claims
- 1176US9395804B2Branch prediction with power usage prediction and controlIBM·Filed 2013·Granted Jul 19, 2016·3 cites·20 claims
- 1275US7079528B2Data communication methodIBM·Filed 2001·Granted Jul 18, 2006·24 cites·22 claims
- 1374US7975172B2Redundant execution of instructions in multistage execution pipeline during unused execution cyclesIBM·Filed 2008·Granted Jul 5, 2011·6 cites·19 claims
- 1474US7814299B2Designating operands with fewer bits in instruction code by indexing into destination register history table for each threadIBM·Filed 2008·Granted Oct 12, 2010·6 cites·1 claims
- 1572US9195463B2Processing core with speculative register preprocessing in unused execution unit cyclesHICKEY MARK J·Filed 2011·Granted Nov 24, 2015·3 cites·25 claims
- 1671US8629867B2Performing vector multiplicationHICKEY MARK J·Filed 2010·Granted Jan 14, 2014·3 cites·17 claims
- 1767US8255674B2Implied storage operation decode using redundant target address detectionHICKEY MARK JOSEPH·Filed 2009·Granted Aug 28, 2012·5 cites·20 claims
- 1866US8028153B2Data dependent instruction decodeIBM·Filed 2008·Granted Sep 27, 2011·3 cites·25 claims
- 1965US7948894B2Data flow control for simultaneous packet receptionIBM·Filed 2008·Granted May 24, 2011·2 cites·12 claims
- 2063US6002333AAlarm system to assist in gauging the size of a door openingFiled 1996·Granted Dec 14, 1999·22 cites·18 claims
- 2161US8522254B2Programmable integrated processor blocksHICKEY MARK J·Filed 2010·Granted Aug 27, 2013·1 cites·18 claims
- 2259US7385925B2Data flow control method for simultaneous packet receptionIBM·Filed 2004·Granted Jun 10, 2008·4 cites·8 claims
- 2353US7187863B2Identifying substreams in parallel/serial data linkIBM·Filed 2001·Granted Mar 6, 2007·2 cites·24 claims
- 2447US7260765B2Methods and apparatus for dynamically reconfigurable parallel data error checkingIBM·Filed 2004·Granted Aug 21, 2007·3 cites·20 claims
- 2547US2006045031A1Automatic hardware data link initialization using multiple state machinesIBM·Filed 2004·Application pending·0 cites
- 2644US10261793B2Instruction predication using instruction address pattern matchingHICKEY MARK J·Filed 2011·Granted Apr 16, 2019·0 cites·18 claims
- 2741US9075599B2Opcode space minimizing architecture utilizing a least significant portion of an instruction address as upper register address bitsHICKEY MARK J·Filed 2010·Granted Jul 7, 2015·0 cites·4 claims
- 2841US2006159023A1CRC error history mechanismIBM·Filed 2005·Application pending·0 cites
- 2940US2007234191A1Methods and apparatus for dynamically reconfigurable parallel data error checkingHICKEY MARK J·Filed 2007·Application pending·0 cites
- 3040US2003112827A1Method and apparatus for deskewing parallel serial data channels using asynchronous elastic buffersIBM·Filed 2001·Application pending·0 cites
- 3132US2013185477A1Variable latency memory delay implementationACUNA VICTOR A·Filed 2012·Application pending·0 cites
- 3231US2013159591A1Verifying data received out-of-order from a busACUNA VICTOR A·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →