Inventor · disambiguated record
Marat Teplitsky
Also filed as: TEPLITSKY MARAT
6 granted patents·57 citations·filing 2007–2014
81Inventor score
Top patents by PatentIndex Score
6 records- 0183US9582406B1Method and system for automatically generating executable system-level testsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Feb 28, 2017·11 cites·18 claims
- 0281US9239773B1Method and system for debugging a program that includes declarative code and procedural codeCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Jan 19, 2016·14 cites·17 claims
- 0380US9514035B1Coverage driven generation of constrained random stimuliCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Dec 6, 2016·8 cites·17 claims
- 0479US8156474B2Automation of software verificationTEPLITSKY MARAT·Filed 2007·Granted Apr 10, 2012·20 cites·18 claims
- 0565US8719771B2Method and system for test reduction and analysisOVADIA MEIR·Filed 2009·Granted May 6, 2014·4 cites·21 claims
- 0638US9189743B1System, method, and computer program product for constraint solvingCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Nov 17, 2015·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →