Inventor · disambiguated record

Manuj Verma

Also filed as: VERMA MANUJ

7 granted patents·73 citations·filing 2005–2020

85Inventor score

Technology areasG06F

Files withCADENCE DESIGN SYSTEMS INC7

Top patents by PatentIndex Score

7 records

0194US10031986B1System and method for creating a spice deck for path-based analysis of an electronic circuit design using a stage-based techniqueCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jul 24, 2018·22 cites·18 claims
0292US9589096B1Method and apparatus for integrating spice-based timing using sign-off path-based analysisCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Mar 7, 2017·12 cites·20 claims
0390US9881123B1Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impactCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jan 30, 2018·12 cites·20 claims
0488US10289774B1Systems and methods for reuse of delay calculation in static timing analysisCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted May 14, 2019·9 cites·20 claims
0587US11023636B1Methods, systems, and computer program product for characterizing an electronic design with a susceptibility windowCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Jun 1, 2021·3 cites·22 claims
0685US9529962B1System and method for generating and using sibling nets model for shared delay calculation across multi-instantiated blocks in the circuit designCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Dec 27, 2016·6 cites·20 claims
0777US7464349B1Method and system or generating a current source model of a gateCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Dec 9, 2008·9 cites·14 claims

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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →