Inventor · disambiguated record
Meir Ovadia
Also filed as: OVADIA MEIR
20 granted patents·1 pending application·135 citations·filing 2007–2019
94Inventor score
Top patents by PatentIndex Score
21 records- 0195US10295596B1Method and system for generating validation testsCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted May 21, 2019·8 cites·9 claims
- 0292US11144693B1Method and system for generating verification tests at runtimeCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Oct 12, 2021·11 cites·17 claims
- 0392US10698805B1Method and system for profiling performance of a system on chipCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Jun 30, 2020·10 cites·15 claims
- 0492US10592703B1Method and system for processing verification tests for testing a design under testCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Mar 17, 2020·9 cites·20 claims
- 0589US10528691B1Method and system for automated selection of a subset of plurality of validation testsCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Jan 7, 2020·6 cites·18 claims
- 0689US9858371B1Method and system for generating post-silicon validation testsCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jan 2, 2018·7 cites·15 claims
- 0787US9792402B1Method and system for debugging a system on chip under testCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Oct 17, 2017·9 cites·13 claims
- 0886US8997049B1Method and system for debugging of compiled code using an interpreterMELNIKOV RODION·Filed 2010·Granted Mar 31, 2015·18 cites·21 claims
- 0984US9690681B1Method and system for automatically generating executable system-level testsCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Jun 27, 2017·8 cites·17 claims
- 1080US10733345B1Method and system for generating a validation testCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Aug 4, 2020·2 cites·17 claims
- 1179US8656368B1System, method, and computer program product for abstract software performance profilingOVADIA MEIR·Filed 2011·Granted Feb 18, 2014·7 cites·18 claims
- 1279US8156474B2Automation of software verificationTEPLITSKY MARAT·Filed 2007·Granted Apr 10, 2012·20 cites·18 claims
- 1377US10698802B1Method and system for generating a validation testCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Jun 30, 2020·2 cites·20 claims
- 1477US10503854B1Method and system for generating validation testsCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Dec 10, 2019·2 cites·19 claims
- 1575US10579761B1Method and system for reconstructing a graph presentation of a previously executed verification testCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Mar 3, 2020·3 cites·20 claims
- 1673US9852046B1Method and system for automated debugging memory allocation and memory releaseCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Dec 26, 2017·2 cites·20 claims
- 1771US9367423B1Methods, systems, and articles of manufacture for using multiple modes during execution of a programOVADIA MEIR·Filed 2011·Granted Jun 14, 2016·5 cites·18 claims
- 1866US9823305B1Method and system for generating post-silicon validation testsCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Nov 21, 2017·2 cites·6 claims
- 1965US8719771B2Method and system for test reduction and analysisOVADIA MEIR·Filed 2009·Granted May 6, 2014·4 cites·21 claims
- 2042US10162920B1System and method for performing out of order name resolution in an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Dec 25, 2018·0 cites·20 claims
- 2142US2014282415A1Method and system for debugging a programCADENCE DESIGN SYSTEMS INC·Filed 2013·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →