Inventor · disambiguated record
Mehmet Can Yildiz
Also filed as: YILDIZ MEHMET · YILDIZ MEHMET C · YILDIZ MEHMET CAN
34 granted patents·2 pending applications·124 citations·filing 2004–2023
96Inventor score
Top patents by PatentIndex Score
36 records- 0196US10963617B1Modifying route topology to fix clock tree violationsCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Mar 30, 2021·11 cites·20 claims
- 0295US11734485B1Routing congestion based on fractional via cost and via densityCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Aug 22, 2023·7 cites·20 claims
- 0393US11030377B1Routing based on pin placement within routing blockageCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Jun 8, 2021·4 cites·20 claims
- 0492US10755024B1System and method for routing in an integrated circuit designCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Aug 25, 2020·13 cites·17 claims
- 0591US10460066B1Routing framework to resolve single-entry constraint violations for integrated circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Oct 29, 2019·9 cites·20 claims
- 0690US10997352B1Routing congestion based on layer-assigned net and placement blockageCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted May 4, 2021·9 cites·11 claims
- 0789US11132489B1Layer assignment based on wirelength thresholdCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Sep 28, 2021·3 cites·20 claims
- 0889US10706201B1Circuit design routing using multi-panel track assignmentCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Jul 7, 2020·6 cites·20 claims
- 0988US10885257B1Routing congestion based on via spacing and pin densityCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Jan 5, 2021·6 cites·14 claims
- 1086US12216977B1Maximum turn constraint for routing of integrated circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Feb 4, 2025·2 cites·20 claims
- 1186US10102328B1System and method for constructing spanning treesCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Oct 16, 2018·5 cites·17 claims
- 1284US12393760B1Wire density-aware layer assignmentCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Aug 19, 2025·1 cites·20 claims
- 1384US10460064B1Partition-aware grid graph based hierarchical global routingCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Oct 29, 2019·4 cites·20 claims
- 1484US10031994B1Systems and methods for congestion and routability aware detailed placementCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jul 24, 2018·5 cites·18 claims
- 1583US10289795B1Routing tree topology generationCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted May 14, 2019·4 cites·20 claims
- 1683US10289792B1Systems and methods for clustering pins for powerCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted May 14, 2019·4 cites·20 claims
- 1780US11928500B1Multi-threaded network routing based on partitioningCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Mar 12, 2024·1 cites·20 claims
- 1877US11030378B1Track assignment by dynamic programmingCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Jun 8, 2021·1 cites·20 claims
- 1977US10685164B1Circuit design routing based on parallel run length rulesCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Jun 16, 2020·2 cites·20 claims
- 2075US10460063B1Integrated circuit routing based on enhanced topologyCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Oct 29, 2019·2 cites·19 claims
- 2172US8271834B2Method and system for providing immunity to computersYILDIZ MEHMET·Filed 2008·Granted Sep 18, 2012·7 cites·15 claims
- 2270US7073144B2Stability metrics for placement to quantify the stability of placement algorithmsIBM·Filed 2004·Granted Jul 4, 2006·14 cites·27 claims
- 2365US8639979B2Method and system for providing immunity to computersYILDIZ MEHMET·Filed 2012·Granted Jan 28, 2014·2 cites·15 claims
- 2459US12505274B1Detecting and modeling via during global routingCADENCE DESIGN SYSTEMS INC·Filed 2023·Granted Dec 23, 2025·0 cites·20 claims
- 2556US8312285B2Global profile management method and systemYILDIZ MEHMET·Filed 2009·Granted Nov 13, 2012·2 cites·20 claims
- 2652US12423499B1Resistance and capacitance aware preferred layer trimmingCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Sep 23, 2025·0 cites·20 claims
- 2752US12393763B1Timing-based layer assignmentCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Aug 19, 2025·0 cites·20 claims
- 2852US12314651B1Zigzag detection and handling for integrated circuit designCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted May 27, 2025·0 cites·20 claims
- 2952US8954802B2Method and system for providing immunity to computersIBM·Filed 2014·Granted Feb 10, 2015·0 cites·15 claims
- 3052US2010106536A1Facilitating electronic knowledge transfer in organizationsYILDIZ MEHMET·Filed 2008·Application pending·0 cites
- 3151US11461530B1Circuit design routing based on routing demand adjustmentCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Oct 4, 2022·0 cites·19 claims
- 3250US12505277B1Cell-based pin access location generationCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Dec 23, 2025·0 cites·20 claims
- 3350US11675955B1Routing using rule-based blockage extensionCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Jun 13, 2023·0 cites·20 claims
- 3446US10460065B1Routing topology generation using spine-like tree structureCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Oct 29, 2019·0 cites·20 claims
- 3543US11080457B1Layer assignment and routing based on resistance or capacitance characteristicCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Aug 3, 2021·0 cites·19 claims
- 3642US2007283301A1System and Method of Eliminating Electrical ViolationsKARANDIKAR ARVIND K·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →