Inventor · disambiguated record
Michael Butts
Also filed as: BUTTS MICHAEL · BUTTS MICHAEL R
52 granted patents·5 pending applications·4,074 citations·filing 1989–2014
99Inventor score
Top patents by PatentIndex Score
57 records- 0199US7948266B2Non-sequentially configurable ICTABULA INC·Filed 2010·Granted May 24, 2011·64 cites·21 claims
- 0298US7667486B2Non-sequentially configurable ICTABULA INC·Filed 2006·Granted Feb 23, 2010·38 cites·15 claims
- 0398US7532032B2Configurable circuits, IC's, and systemsTABULA INC·Filed 2006·Granted May 12, 2009·71 cites·20 claims
- 0498US7193440B1Configurable circuits, IC's, and systemsSCHMIT HERMAN·Filed 2004·Granted Mar 20, 2007·125 cites·23 claims
- 0598US7109752B1Configurable circuits, IC's, and systemsSCHMIT HERMAN·Filed 2004·Granted Sep 19, 2006·124 cites·45 claims
- 0698US6732068B2Memory circuit for use in hardware emulation systemQUICKTURN DESIGN SYSTEMS INC·Filed 2001·Granted May 4, 2004·273 cites·4 claims
- 0798US6020760AI/O buffer circuit with pin multiplexingALTERA CORP·Filed 1997·Granted Feb 1, 2000·202 cites·23 claims
- 0898US5960191AEmulation system with time-multiplexed interconnectQUICKTURN DESIGN SYSTEMS INC·Filed 1997·Granted Sep 28, 1999·169 cites·25 claims
- 0998US5036473AMethod of using electronically reconfigurable logic circuitsMENTOR GRAPHICS CORP·Filed 1989·Granted Jul 30, 1991·428 cites·19 claims
- 1097US7616027B2Configurable circuits, IC's and systemsTABULA INC·Filed 2006·Granted Nov 10, 2009·35 cites·18 claims
- 1197US7167025B1Non-sequentially configurable ICSCHMIT HERMAN·Filed 2004·Granted Jan 23, 2007·69 cites·22 claims
- 1297US6377912B1Emulation system with time-multiplexed interconnectQUICKTURN DESIGN SYSTEMS INC·Filed 1999·Granted Apr 23, 2002·153 cites·45 claims
- 1397US6285211B1I/O buffer circuit with pin multiplexingALTERA CORP·Filed 1999·Granted Sep 4, 2001·131 cites·19 claims
- 1497US5452231AHierarchically connected reconfigurable logic assemblyQUICKTURN DESIGN SYSTEMS INC·Filed 1994·Granted Sep 19, 1995·224 cites·13 claims
- 1597US5448496APartial crossbar interconnect architecture for reconfigurably connecting multiple reprogrammable logic devices in a logic emulation systemQUICKTURN DESIGN SYSTEMS INC·Filed 1994·Granted Sep 5, 1995·207 cites·23 claims
- 1696US8305110B2Non-sequentially configurable ICSCHMIT HERMAN·Filed 2011·Granted Nov 6, 2012·16 cites·29 claims
- 1796US8193830B2Configurable circuits, IC's, and systemsSCHMIT HERMAN·Filed 2010·Granted Jun 5, 2012·16 cites·18 claims
- 1896US7872496B2Method of mapping a user design defined for a user design cycle to an IC with multiple sub-cycle reconfigurable circuitsTABULA INC·Filed 2008·Granted Jan 18, 2011·24 cites·20 claims
- 1996US7157933B1Configurable circuits, IC's, and systemsSCHMIT HERMAN·Filed 2004·Granted Jan 2, 2007·79 cites·55 claims
- 2096US6353552B2PLD with on-chip memory having a shadow registerALTERA CORP·Filed 2001·Granted Mar 5, 2002·56 cites·54 claims
- 2196US6184707B1Look-up table based logic element with complete permutability of the inputs to the secondary signalsALTERA CORP·Filed 1998·Granted Feb 6, 2001·257 cites·27 claims
- 2295US7425841B2Configurable circuits, IC's, and systemsTABULA INC·Filed 2004·Granted Sep 16, 2008·48 cites·30 claims
- 2394US6011744AProgrammable logic device with multi-port memoryALTERA CORP·Filed 1997·Granted Jan 4, 2000·69 cites·11 claims
- 2493US7408382B2Configurable circuits, IC's, and systemsTABULA INC·Filed 2006·Granted Aug 5, 2008·23 cites·20 claims
- 2593US6317367B1FPGA with on-chip multiport memoryALTERA CORP·Filed 2000·Granted Nov 13, 2001·37 cites·128 claims
- 2691US8638119B2Configurable circuits, IC's, and systemsSCHMIT HERMAN·Filed 2012·Granted Jan 28, 2014·7 cites·19 claims
- 2791US6539535B2Programmable logic device having integrated probing structuresQUICKTURN DESIGN SYSTEMS INC·Filed 2001·Granted Mar 25, 2003·80 cites·15 claims
- 2891US6002861AMethod for performing simulation using a hardware emulation systemQUICKTURN DESIGN SYSTEMS INC·Filed 1998·Granted Dec 14, 1999·109 cites·3 claims
- 2991US5821773ALook-up table based logic element with complete permutability of the inputs to the secondary signalsALTERA CORP·Filed 1995·Granted Oct 13, 1998·71 cites·32 claims
- 3091US5612891AHardware logic emulation system with memory capabilityQUICKTURN DESIGN SYSTEMS INC·Filed 1995·Granted Mar 18, 1997·120 cites·10 claims
- 3190US5870410ADiagnostic interface system for programmable logic system developmentALTERA CORP·Filed 1997·Granted Feb 9, 1999·83 cites·13 claims
- 3289US5661662AStructures and methods for adding stimulus and response functions to a circuit design undergoing emulationQUICKTURN DESIGN SYSTEMS INC·Filed 1995·Granted Aug 26, 1997·102 cites·1 claims
- 3387US7739097B2Emulation system with time-multiplexed interconnectQUICKTURN DESIGN SYSTEMS INC·Filed 2002·Granted Jun 15, 2010·26 cites·17 claims
- 3486US5812414AMethod for performing simulation using a hardware logic emulation systemQUICKTURN DESIGN SYSTEMS INC·Filed 1996·Granted Sep 22, 1998·77 cites·8 claims
- 3585US8810277B2Non-sequentially configurable ICSCHMIT HERMAN·Filed 2012·Granted Aug 19, 2014·4 cites·20 claims
- 3682US6011730AProgrammable logic device with multi-port memoryALTERA CORP·Filed 1999·Granted Jan 4, 2000·31 cites·42 claims
- 3782US5796623AApparatus and method for performing computations with electrically reconfigurable logic devicesQUICKTURN DESIGN SYSTEMS INC·Filed 1996·Granted Aug 18, 1998·60 cites·2 claims
- 3879US7260794B2Logic multiprocessor for FPGA implementationQUICKTURN DESIGN SYSTEMS INC·Filed 2003·Granted Aug 21, 2007·27 cites·8 claims
- 3979US6289494B1Optimized emulation and prototyping architectureQUICKTURN DESIGN SYSTEMS INC·Filed 1997·Granted Sep 11, 2001·78 cites·10 claims
- 4078US6625793B2Optimized emulation and prototyping architectureQUICKTURN DESIGN SYSTEMS INC·Filed 2001·Granted Sep 23, 2003·23 cites·1 claims
- 4178US6570404B1High-performance programmable logic architectureALTERA CORP·Filed 1997·Granted May 27, 2003·29 cites·38 claims
- 4278US5657241ARouting methods for use in a logic emulation systemQUICKTURN DESIGN SYSTEMS INC·Filed 1995·Granted Aug 12, 1997·52 cites·1 claims
- 4375US6882176B1High-performance programmable logic architectureQUICKTURN DESIGN SYSTEMS INC·Filed 2003·Granted Apr 19, 2005·14 cites·29 claims
- 4473US5734581AMethod for implementing tri-state nets in a logic emulation systemQUICKTURN DESIGN SYSTEMS INC·Filed 1996·Granted Mar 31, 1998·37 cites·2 claims
- 4572US7792933B2System and method for performing design verificationCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Sep 7, 2010·18 cites·29 claims
- 4672US6034857AInput/output buffer with overcurrent protection circuitALTERA CORP·Filed 1997·Granted Mar 7, 2000·22 cites·4 claims
- 4771US6810373B1Method and apparatus for modeling using a hardware-software co-verification environmentSYNOPSIS INC·Filed 2000·Granted Oct 26, 2004·29 cites·27 claims
- 4870US8103866B2System for reconfiguring a processor arrayBUTTS MICHAEL R·Filed 2008·Granted Jan 24, 2012·6 cites·13 claims
- 4969US6151258AProgrammable logic device with multi-port memoryQUICKTURN DESIGN SYSTEMS INC·Filed 1999·Granted Nov 21, 2000·13 cites·18 claims
- 5062US6259588B1Input/output buffer with overcurrent protection circuitALTERA CORP·Filed 1999·Granted Jul 10, 2001·14 cites·11 claims
Showing the top 50 of 57 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →