Method for performing simulation using a hardware emulation system

Abstract

A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.

We claim: 
     
       1. A method of simulating a functional circuit design, the functional circuit design comprising logic elements, the logic elements comprising outputs, the method comprising: (a) configuring a reconfigurable logic apparatus to implement the functional circuit, said reconfigurable logic apparatus comprising N reconfigurable logic devices, where N is a number greater than one, said functional circuit being implemented by at least two of said N reconfigurable logic devices, thereby creating an emulation design;   (b) loading the functional circuit into an event-driven software simulator;   (c) stimulating said emulation design configured into said reconfigurable logic apparatus with stimulus signals until immediately prior to a predetermined event taking place;   (d) stopping said stimulating of said emulation design;   (e) reading state data from the outputs of the logic elements of the functional circuit design created by said emulated design in said reconfigurable logic apparatus;   (f) initializing the functional circuit loaded into said event-driven software simulator with said state data read from said reconfigurable logic apparatus; and   (g) simulating said functional circuit in said event-driven software simulator using said state data as stimulus.   
     
     
       2. The method of claim 1 wherein steps (a) and (b) take place at substantially the same time. 
     
     
       3. The method of claim 1 wherein steps (a) through (g) are performed in seriatim.