Inventor · disambiguated record
Jon A. Batcheller
Also filed as: BATCHELLER JON A
10 granted patents·1,416 citations·filing 1989–1998
94Inventor score
Technology areasG06F
Top patents by PatentIndex Score
10 records- 0198US5036473AMethod of using electronically reconfigurable logic circuitsMENTOR GRAPHICS CORP·Filed 1989·Granted Jul 30, 1991·428 cites·19 claims
- 0297US5452231AHierarchically connected reconfigurable logic assemblyQUICKTURN DESIGN SYSTEMS INC·Filed 1994·Granted Sep 19, 1995·224 cites·13 claims
- 0397US5448496APartial crossbar interconnect architecture for reconfigurably connecting multiple reprogrammable logic devices in a logic emulation systemQUICKTURN DESIGN SYSTEMS INC·Filed 1994·Granted Sep 5, 1995·207 cites·23 claims
- 0491US6002861AMethod for performing simulation using a hardware emulation systemQUICKTURN DESIGN SYSTEMS INC·Filed 1998·Granted Dec 14, 1999·109 cites·3 claims
- 0591US5612891AHardware logic emulation system with memory capabilityQUICKTURN DESIGN SYSTEMS INC·Filed 1995·Granted Mar 18, 1997·120 cites·10 claims
- 0689US5661662AStructures and methods for adding stimulus and response functions to a circuit design undergoing emulationQUICKTURN DESIGN SYSTEMS INC·Filed 1995·Granted Aug 26, 1997·102 cites·1 claims
- 0786US5812414AMethod for performing simulation using a hardware logic emulation systemQUICKTURN DESIGN SYSTEMS INC·Filed 1996·Granted Sep 22, 1998·77 cites·8 claims
- 0882US5796623AApparatus and method for performing computations with electrically reconfigurable logic devicesQUICKTURN DESIGN SYSTEMS INC·Filed 1996·Granted Aug 18, 1998·60 cites·2 claims
- 0978US5657241ARouting methods for use in a logic emulation systemQUICKTURN DESIGN SYSTEMS INC·Filed 1995·Granted Aug 12, 1997·52 cites·1 claims
- 1073US5734581AMethod for implementing tri-state nets in a logic emulation systemQUICKTURN DESIGN SYSTEMS INC·Filed 1996·Granted Mar 31, 1998·37 cites·2 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →