Inventor · disambiguated record
Michael Hargrove
Also filed as: HARGROVE MICHAEL · HARGROVE MICHAEL J · HARGROVE MICHAEL JOHN
58 granted patents·12 pending applications·1,097 citations·filing 1993–2015
99Inventor score
Top patents by PatentIndex Score
70 records- 0198US9343300B1Methods of forming source/drain regions for a PMOS transistor device with a germanium-containing channel regionGLOBALFOUNDRIES INC·Filed 2015·Granted May 17, 2016·45 cites·18 claims
- 0297US9318342B2Methods of removing fins for finfet semiconductor devicesGLOBALFOUNDRIES INC·Filed 2015·Granted Apr 19, 2016·16 cites·12 claims
- 0397US8048791B2Method of forming a semiconductor deviceGLOBALFOUNDRIES INC·Filed 2009·Granted Nov 1, 2011·122 cites·17 claims
- 0496US9147730B2Methods of forming fins for FinFET semiconductor devices and selectively removing some of the fins by performing a cyclical fin cutting processGLOBALFOUNDRIES INC·Filed 2014·Granted Sep 29, 2015·25 cites·20 claims
- 0595US8361894B1Methods of forming FinFET semiconductor devices with different fin heightsGLOBALFOUNDRIES INC·Filed 2012·Granted Jan 29, 2013·34 cites·18 claims
- 0694US7932143B1Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methodsGLOBALFOUNDRIES INC·Filed 2009·Granted Apr 26, 2011·32 cites·17 claims
- 0793US6531375B1Method of forming a body contact using BOX modificationIBM·Filed 2001·Granted Mar 11, 2003·78 cites·13 claims
- 0892US8076209B2Methods for fabricating MOS devices having highly stressed channelsYANG FRANK BIN·Filed 2010·Granted Dec 13, 2011·17 cites·20 claims
- 0992US6372559B1Method for self-aligned vertical double-gate MOSFETIBM·Filed 2000·Granted Apr 16, 2002·121 cites·22 claims
- 1091US7268645B2Integrated resonator structure and methods for its manufacture and useSEIKO EPSON CORP·Filed 2005·Granted Sep 11, 2007·20 cites·24 claims
- 1191US6433587B1SOI CMOS dynamic circuits having threshold voltage controlIBM·Filed 2000·Granted Aug 13, 2002·44 cites·12 claims
- 1290US7767534B2Methods for fabricating MOS devices having highly stressed channelsADVANCED MICRO DEVICES INC·Filed 2008·Granted Aug 3, 2010·16 cites·13 claims
- 1390US7723192B2Integrated circuit long and short channel metal gate devices and method of manufactureADVANCED MICRO DEVICES INC·Filed 2008·Granted May 25, 2010·16 cites·19 claims
- 1489US8809178B2Methods of forming bulk FinFET devices with replacement gates so as to reduce punch through leakage currentsLIU YANXIANG·Filed 2012·Granted Aug 19, 2014·13 cites·20 claims
- 1589US8294211B2Semiconductor transistor device structure with back side gate contact plugs, and related manufacturing methodYANG BIN·Filed 2010·Granted Oct 23, 2012·11 cites·11 claims
- 1689US7598838B2Variable inductor techniqueSEIKO EPSON CORP·Filed 2005·Granted Oct 6, 2009·21 cites·17 claims
- 1788US7939852B2Transistor device having asymmetric embedded strain elements and related manufacturing methodGLOBALFOUNDRIES INC·Filed 2008·Granted May 10, 2011·10 cites·10 claims
- 1887US7998832B2Semiconductor device with isolation trench liner, and related fabrication methodsADVANCED MICRO DEVICES INC·Filed 2008·Granted Aug 16, 2011·11 cites·6 claims
- 1986US8026539B2Metal oxide semiconductor devices having doped silicon-compromising capping layers and methods for fabricating the sameGLOBALFOUNDRIES INC·Filed 2009·Granted Sep 27, 2011·13 cites·23 claims
- 2086US7994014B2Semiconductor devices having faceted silicide contacts, and related fabrication methodsADVANCED MICRO DEVICES INC·Filed 2008·Granted Aug 9, 2011·11 cites·5 claims
- 2185US8716828B2Semiconductor device with isolation trench linerCARTER RICHARD J·Filed 2012·Granted May 6, 2014·6 cites·18 claims
- 2285US8039349B2Methods for fabricating non-planar semiconductor devices having stress memoryGLOBALFOUNDRIES INC·Filed 2009·Granted Oct 18, 2011·9 cites·4 claims
- 2385US7977174B2FinFET structures with stress-inducing source/drain-forming spacers and methods for fabricating the sameGLOBALFOUNDRIES INC·Filed 2009·Granted Jul 12, 2011·11 cites·20 claims
- 2484US8148750B2Transistor device having asymmetric embedded strain elements and related manufacturing methodPAL ROHIT·Filed 2011·Granted Apr 3, 2012·5 cites·9 claims
- 2584US6320225B1SOI CMOS body contact through gate, self-aligned to source- drain diffusionsIBM·Filed 1999·Granted Nov 20, 2001·74 cites·9 claims
- 2683US8569810B2Metal semiconductor alloy contact with low resistanceYU JIAN·Filed 2010·Granted Oct 29, 2013·6 cites·9 claims
- 2783US7902599B2Integrated circuit having long and short channel metal gate devices and method of manufactureADVANCED MICRO DEVICES INC·Filed 2009·Granted Mar 8, 2011·8 cites·19 claims
- 2882US5401130AInternal circulation fluidized bed (ICFB) combustion system and method of operation thereofCOMBUSTION ENG·Filed 1993·Granted Mar 28, 1995·32 cites·16 claims
- 2981US9472554B2Integrated circuits having FinFET semiconductor devices and methods of fabricating the same to resist sub-fin current leakageGLOBALFOUNDRIES INC·Filed 2013·Granted Oct 18, 2016·6 cites·12 claims
- 3080US6756637B2Method of controlling floating body effects in an asymmetrical SOI deviceIBM·Filed 2001·Granted Jun 29, 2004·22 cites·10 claims
- 3179US7157926B1Universal padset concept for high-frequency probingSEIKO EPSON CORP·Filed 2005·Granted Jan 2, 2007·14 cites·20 claims
- 3279US5731941AElectrostatic discharge suppression circuit employing trench capacitorIBM·Filed 1995·Granted Mar 24, 1998·44 cites·21 claims
- 3378US9437740B2Epitaxially forming a set of fins in a semiconductor deviceGLOBALFOUNDRIES INC·Filed 2015·Granted Sep 6, 2016·2 cites·7 claims
- 3477US6335262B1Method for fabricating different gate oxide thicknesses within the same chipIBM·Filed 1999·Granted Jan 1, 2002·46 cites·8 claims
- 3576US8217472B2Semiconductor device with isolation trench linerCARTER RICHARD J·Filed 2011·Granted Jul 10, 2012·3 cites·7 claims
- 3674US7183175B2Shallow trench isolation structure for strained Si on SiGeIBM·Filed 2005·Granted Feb 27, 2007·5 cites·12 claims
- 3773US7315438B2Technique to reduce ESD loading capacitanceSEIKO EPSON CORP·Filed 2003·Granted Jan 1, 2008·19 cites·48 claims
- 3871US7224180B2Methods and systems for rise-time improvements in differential signal outputsSEIKO EPSON CORP·Filed 2004·Granted May 29, 2007·14 cites·23 claims
- 3970US9236258B2Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devicesGLOBALFOUNDRIES INC·Filed 2014·Granted Jan 12, 2016·2 cites·16 claims
- 4070US7384857B2Method to fabricate completely isolated silicon regionsSEIKO EPSON CORP·Filed 2005·Granted Jun 10, 2008·3 cites·22 claims
- 4169US8987078B2Metal semiconductor alloy contact with low resistanceIBM·Filed 2013·Granted Mar 24, 2015·2 cites·19 claims
- 4269US6531741B1Dual buried oxide film SOI structure and method of manufacturing the sameIBM·Filed 1999·Granted Mar 11, 2003·34 cites·25 claims
- 4368US9312387B2Methods of forming FinFET devices with alternative channel materialsGLOBALFOUNDRIES INC·Filed 2013·Granted Apr 12, 2016·2 cites·20 claims
- 4468US8217463B2Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methodsPAL ROHIT·Filed 2011·Granted Jul 10, 2012·2 cites·20 claims
- 4566US9034737B2Epitaxially forming a set of fins in a semiconductor deviceGLOBALFOUNDRIES INC·Filed 2013·Granted May 19, 2015·1 cites·20 claims
- 4666US8373228B2Semiconductor transistor device structure with back side source/drain contact plugs, and related manufacturing methodGLOBALFOUNDRIES INC·Filed 2010·Granted Feb 12, 2013·2 cites·14 claims
- 4766US8293609B2Method of manufacturing a transistor device having asymmetric embedded strain elementsPAL ROHIT·Filed 2012·Granted Oct 23, 2012·1 cites·12 claims
- 4864US6344671B1Pair of FETs including a shared SOI body contact and the method of forming the FETsIBM·Filed 1999·Granted Feb 5, 2002·19 cites·19 claims
- 4962US7632727B2Method of forming stepped recesses for embedded strain elements in a semiconductor deviceGLOBALFOUNDRIES INC·Filed 2008·Granted Dec 15, 2009·1 cites·14 claims
- 5061US9530864B2Junction overlap control in a semiconductor device using a sacrificial spacer layerGLOBALFOUNDRIES INC·Filed 2014·Granted Dec 27, 2016·1 cites·20 claims
Showing the top 50 of 70 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →