Inventor · disambiguated record
Michael D. Upton
Also filed as: UPTON MICHAEL · UPTON MICHAEL D
23 granted patents·4 pending applications·905 citations·filing 1992–2023
97Inventor score
Technology areasG06F
Top patents by PatentIndex Score
27 records- 0191US6370625B1Method and apparatus for lock synchronization in a microprocessor systemINTEL CORP·Filed 1999·Granted Apr 9, 2002·189 cites·27 claims
- 0287US6651158B2Determination of approaching instruction starvation of threads based on a plurality of conditionsINTEL CORP·Filed 2001·Granted Nov 18, 2003·39 cites·30 claims
- 0385US6735688B1Processor having replay architecture with fast and slow replay pathsINTEL CORP·Filed 2000·Granted May 11, 2004·41 cites·23 claims
- 0484US6018786ATrace based instruction cachingINTEL CORP·Filed 1997·Granted Jan 25, 2000·107 cites·46 claims
- 0584US5351197AMethod and apparatus for designing the layout of a subcircuit in an integrated circuitCASCADE DESIGN AUTOMATION·Filed 1992·Granted Sep 27, 1994·159 cites·9 claims
- 0682US6643747B2Processing requests to efficiently access a limited bandwidth storage areaINTEL CORP·Filed 2000·Granted Nov 4, 2003·34 cites·25 claims
- 0781US9465670B2Generational thread scheduler using reservations for fair schedulingGROCHOWSKI EDWARD T·Filed 2011·Granted Oct 11, 2016·7 cites·20 claims
- 0880US6487675B2Processor having execution core sections operating at different clock ratesINTEL CORP·Filed 2001·Granted Nov 26, 2002·21 cites·53 claims
- 0973US6256745B1Processor having execution core sections operating at different clock ratesINTEL CORP·Filed 2000·Granted Jul 3, 2001·13 cites·21 claims
- 1073US6170038B1Trace based instruction cachingINTEL CORP·Filed 1999·Granted Jan 2, 2001·60 cites·18 claims
- 1172US7987346B2Method and apparatus for assigning thread priority in a processor or the likeINTEL CORP·Filed 2011·Granted Jul 26, 2011·2 cites·32 claims
- 1272US7454600B2Method and apparatus for assigning thread priority in a processor or the likeINTEL CORP·Filed 2001·Granted Nov 18, 2008·12 cites·12 claims
- 1372US6216234B1Processor having execution core sections operating at different clock ratesINTEL CORP·Filed 1998·Granted Apr 10, 2001·49 cites·9 claims
- 1471US7010669B2Determining whether thread fetch operation will be blocked due to processing of another threadINTEL CORP·Filed 2003·Granted Mar 7, 2006·13 cites·9 claims
- 1570US6094717AComputer processor with a replay system having a plurality of checkersINTEL CORP·Filed 1998·Granted Jul 25, 2000·55 cites·30 claims
- 1667US5828868AProcessor having execution core sections operating at different clock ratesINTEL CORP·Filed 1996·Granted Oct 27, 1998·38 cites·4 claims
- 1766US6138225AAddress translation system having first and second translation look aside buffersINTEL CORP·Filed 1997·Granted Oct 24, 2000·56 cites·29 claims
- 1863US9785436B2Apparatus and method for efficient gather and scatter operationsINTEL CORP·Filed 2012·Granted Oct 10, 2017·1 cites·26 claims
- 1960USRE44494EProcessor having execution core sections operating at different clock ratesSAGER DAVID J·Filed 2004·Granted Sep 10, 2013·5 cites·55 claims
- 2056USRE45487EProcessor having execution core sections operating at different clock ratesINTEL CORP·Filed 2013·Granted Apr 21, 2015·0 cites·75 claims
- 2155US7877583B2Method and apparatus for assigning thread priority in a processor or the likeINTEL CORP·Filed 2008·Granted Jan 25, 2011·0 cites·22 claims
- 2253US2025004781A1Method and apparatus to implement adaptive branch prediction throttlingINTEL CORP·Filed 2023·Application pending·0 cites
- 2352US8850165B2Method and apparatus for assigning thread priority in a processor or the likeBURNS DAVID W·Filed 2011·Granted Sep 30, 2014·0 cites·15 claims
- 2450US7085889B2Use of a context identifier in a cache memoryINTEL CORP·Filed 2002·Granted Aug 1, 2006·4 cites·10 claims
- 2549US2017031729A1Generational Thread SchedulerINTEL CORP·Filed 2016·Application pending·0 cites
- 2648US2012042151A1Processor having execution core sections operating at different clock ratesSAGER DAVID J·Filed 2010·Application pending·0 cites
- 2740US2003177312A1Controlling a store data forwarding mechanism during execution of a load operationFiled 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →