Processor having execution core sections operating at different clock rates

Abstract

A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.

We claim: 
     
         1 - 64 . (canceled) 
     
     
         65 . An integrated circuit comprising:
 logic to perform input/output (I/O) operations at a first frequency;   an arithmetic logic unit (ALU) to operate at a second frequency; and   a floating-point unit (FPU) to operate at a third frequency, the third frequency being different than the second frequency.   
     
     
         66 . The integrated circuit of  claim 65 , wherein the third frequency is half of the second frequency. 
     
     
         67 . The integrated circuit of  claim 66 , further comprising an integer register file coupled to the ALU to operate at the second frequency and a floating point register file coupled to the FPU to operate at the third frequency. 
     
     
         68 . The integrated circuit of  claim 67 , further comprising:
 an instruction cache to cache fetched instructions;   a renamer unit to rename specific registers indicated by instructions;   a scheduler unit to reorder instructions; and   a look-aside buffer to provide physical addresses of data operands;   the instruction cache, renamer unit, scheduler unit, and look-aside buffer to operate at a fourth frequency.   
     
     
         69 . The integrated circuit of  claim 68 , wherein the fourth frequency is the same as the second frequency. 
     
     
         70 . The integrated circuit of  claim 68 , wherein the fourth frequency is slower than the third frequency. 
     
     
         71 . The integrated circuit of  claim 65 , wherein I/O operations are selected from a group consisting of buffering data, buffering instructions, receiving data, receiving instructions, parity checking, and communicating with external devices. 
     
     
         72 . The integrated circuit of  claim 65 , wherein the third frequency is substantially 0 MHz when the FPU is powered down. 
     
     
         73 . The integrated circuit of  claim 65 , wherein the second frequency is substantially 0 MHz when the ALU is powered down. 
     
     
         74 . An integrated circuit comprising:
 logic to perform input/output (I/O) operations at a first frequency;   a first arithmetic logic unit (ALU), a first data cache, and a first register file to operate at a second clock frequency; and   a second ALU, a second register file, and a second data cache to operate at a third clock frequency, the third clock frequency being different then the second clock frequency.   
     
     
         75 . The integrated circuit of  claim 74 , further comprising a floating-point unit (FPU) to operate at the third clock frequency. 
     
     
         76 . The integrated circuit of  claim 75 , wherein the second ALU, second data cache, second register file, and the FPU are not nested within the first ALU, first data cache, and first register file. 
     
     
         77 . The integrated circuit of  claim 75 , wherein the third clock frequency is faster then the second clock frequency. 
     
     
         78 . The integrated circuit of  claim 74 , wherein the second clock frequency is a multiple of N of the third clock frequency. 
     
     
         79 . The integrated circuit of  claim 74 , wherein the second clock frequency is substantially 0 when the first ALU, first data cache, and first register file are powered down, the third clock frequency being an integer multiple of the first clock frequency. 
     
     
         80 . The integrated circuit of  claim 74 , further comprising:
 a look-aside buffer operating at a fourth frequency, the look-aside buffer having a first partition dedicated to the first ALU, first data cache, and first register file and a second partition dedicated to the second ALU, second data cache, and second register file.   
     
     
         81 . The integrated circuit of  claim 74 , further comprising:
 a first look-aside buffer, a first renamer unit, a first scheduler unit, and a first hit/miss unit operating at the second frequency; and   a second look-aside buffer, a second renamer unit, a second scheduler unit, and a second hit/miss unit operating at the third frequency.   
     
     
         82 . A microprocessor comprising:
 a fetch unit and a decoder to operate at a first frequency;   a multiplier and a first shifter to operate at a second frequency; and   an adder and logic to perform AND and OR operations to operate at a third frequency, the third frequency being different from the second frequency.   
     
     
         83 . The microprocessor of  claim 82 , wherein first frequency is lower than the second frequency, and wherein the third frequency is an integer multiple of the second frequency. 
     
     
         84 . The microprocessor of  claim 83 , wherein the third frequency is higher than the second frequency by a factor of 2. 
     
     
         85 . The microprocessor of  claim 84 , wherein the second and third frequencies are not integer multiples of the first frequency. 
     
     
         86 . The microprocessor of  claim 84 , further comprising:
 a register file, the register file coupled to the adder and to the logic; and   a second shifter;   the register file and the second shifter to operate at the third frequency.   
     
     
         87 . The microprocessor of  claim 84 , further comprising an instruction cache and a register file to operate at the first frequency.