Inventor · disambiguated record
Moez Cherif
Also filed as: CHERIF MOEZ
16 granted patents·5 pending applications·78 citations·filing 2019–2025
91Inventor score
Files withARTERIS INC21
Top patents by PatentIndex Score
21 records- 0197US11449655B2Synthesis of a network-on-chip (NoC) using performance constraints and objectivesARTERIS INC·Filed 2020·Granted Sep 20, 2022·18 cites·17 claims
- 0296US11121933B2Physically aware topology synthesis of a networkARTERIS INC·Filed 2019·Granted Sep 14, 2021·27 cites·14 claims
- 0396US10990724B1System and method for incremental topology synthesis of a network-on-chipARTERIS INC·Filed 2019·Granted Apr 27, 2021·24 cites·8 claims
- 0488US12237980B2Topology synthesis of a network-on-chip (NoC)ARTERIS INC·Filed 2021·Granted Feb 25, 2025·2 cites·15 claims
- 0588US11836427B2Constraints and objectives used in synthesis of a network-on-chip (NoC)ARTERIS INC·Filed 2022·Granted Dec 5, 2023·1 cites·10 claims
- 0688US11601357B2System and method for generation of quality metrics for optimization tasks in topology synthesis of a networkARTERIS INC·Filed 2020·Granted Mar 7, 2023·2 cites·5 claims
- 0787US11657203B2Multi-phase topology synthesis of a network-on-chip (NoC)ARTERIS INC·Filed 2020·Granted May 23, 2023·2 cites·10 claims
- 0884US11665776B2System and method for synthesis of a network-on-chip for deadlock-free transformationARTERIS INC·Filed 2020·Granted May 30, 2023·2 cites·19 claims
- 0983US2025373572A1DESIGN TOOL FOR GENERATION OF DEADLOCK FREE NETWORK-ON-CHIP (NoC) WITHIN A SYSTEM-ON-CHIP (SoC)ARTERIS INC·Filed 2025·Application pending·0 cites
- 1081US2025293940A1MODIFICATION OF EXISTING NETWORK-ON-CHIPs (NoCs) USING INCREMENTAL MODIFICATIONSARTERIS INC·Filed 2025·Application pending·0 cites
- 1180US12348382B2Incremental topology modification of a network-on-chipARTERIS INC·Filed 2024·Granted Jul 1, 2025·0 cites·1 claims
- 1279US12204833B2System and method to generate a network-on-chip (NoC) description using incremental topology synthesisARTERIS INC·Filed 2023·Granted Jan 21, 2025·0 cites·11 claims
- 1378US12135928B2Constraints and objectives used in synthesis of a network-on-chip (NoC)ARTERIS INC·Filed 2023·Granted Nov 5, 2024·0 cites·7 claims
- 1474US2025233833A1SYSTEM AND METHOD FOR DEADLOCK DETECTION IN NETWORK-ON-CHIP (NoC) HAVING EXTERNAL DEPENDENCIESARTERIS INC·Filed 2025·Application pending·0 cites
- 1574US2025156616A1System and method to generate a network-on-chip topology using incremental synthesisARTERIS INC·Filed 2025·Application pending·0 cites
- 1672US2025265404A1ELECTRONIC DESIGN TOLL FOR GENERATION OF A NETWORK-ON-CHIP (NoC)ARTERIS INC·Filed 2025·Application pending·0 cites
- 1770US11956127B2Incremental topology modification of a network-on-chipARTERIS INC·Filed 2022·Granted Apr 9, 2024·0 cites·17 claims
- 1870US11748535B2System and method to generate a network-on-chip (NoC) description using incremental topology synthesisARTERIS INC·Filed 2021·Granted Sep 5, 2023·0 cites·14 claims
- 1969US12438829B2System and method for deadlock detection in network-on-chip (NoC) having external dependenciesARTERIS INC·Filed 2022·Granted Oct 7, 2025·0 cites·7 claims
- 2069US11784909B2Quality metrics for optimization tasks in generation of a networkARTERIS INC·Filed 2023·Granted Oct 10, 2023·0 cites·7 claims
- 2148US11558259B2System and method for generating and using physical roadmaps in network synthesisARTERIS INC·Filed 2020·Granted Jan 17, 2023·0 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →