Inventor · disambiguated record
Mohammad Hasan
Also filed as: HASAN MOHAMMAD · HASAN MOHAMMAD R
13 granted patents·36 pending applications·6 citations·filing 2019–2025
83Inventor score
Top patents by PatentIndex Score
49 records- 0188US12364002B2Integrated circuit structures having metal gates with tapered plugsINTEL CORP·Filed 2021·Granted Jul 15, 2025·2 cites·20 claims
- 0284US11804523B2High aspect ratio source or drain structures with abrupt dopant profileINTEL CORP·Filed 2019·Granted Oct 31, 2023·3 cites·18 claims
- 0383US2025331300A1Integrated circuit structures having cut metal gatesINTEL CORP·Filed 2025·Application pending·0 cites
- 0481US2025133821A1Integrated circuit structures having cut metal gatesINTEL CORP·Filed 2024·Application pending·0 cites
- 0579US12176408B2Localized spacer for nanowire transistors and methods of fabricationINTEL CORP·Filed 2020·Granted Dec 24, 2024·1 cites·15 claims
- 0679US2024347539A1Integrated circuit structures having cut metal gatesINTEL CORP·Filed 2024·Application pending·0 cites
- 0775US12369392B2Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gatesINTEL CORP·Filed 2024·Granted Jul 22, 2025·0 cites·20 claims
- 0875US12288808B2High aspect ratio source or drain structures with abrupt dopant profileINTEL CORP·Filed 2023·Granted Apr 29, 2025·0 cites·20 claims
- 0972US2025227991A1Integrated circuit structures with backside gate partial cut or trench contact partial cutINTEL CORP·Filed 2025·Application pending·0 cites
- 1071US2025227988A1Integrated circuit structures having dielectric gate wall and dielectric gate plugINTEL CORP·Filed 2025·Application pending·0 cites
- 1170US2024154037A1Integrated circuit structures having dielectric anchor and confined epitaxial source or drain structureINTEL CORP·Filed 2023·Application pending·0 cites
- 1269US2022392898A1Integrated circuit structures having cut metal gatesINTEL CORP·Filed 2021·Application pending·0 cites
- 1366US12507464B2Gate aligned fin cut for advanced integrated circuit structure fabricationINTEL CORP·Filed 2021·Granted Dec 23, 2025·0 cites·10 claims
- 1466US2023197854A1Integrated circuit structures having dielectric anchor and confined epitaxial source or drain structureINTEL CORP·Filed 2021·Application pending·0 cites
- 1565US12364001B2Integrated circuit structures with backside gate partial cut or trench contact partial cutINTEL CORP·Filed 2021·Granted Jul 15, 2025·0 cites·10 claims
- 1663US2023197855A1Gate-all-around integrated circuit structures having source or drain structures with regrown central portionsHASAN MOHAMMAD·Filed 2021·Application pending·0 cites
- 1761US11990472B2Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gatesINTEL CORP·Filed 2020·Granted May 21, 2024·0 cites·11 claims
- 1860US2023093657A1Integrated circuit structures having dielectric gate wall and dielectric gate plugINTEL CORP·Filed 2021·Application pending·0 cites
- 1959US2023178622A1Gate-all-around integrated circuit structures having depopulated channel structures using directed bottom-up approachINTEL CORP·Filed 2021·Application pending·0 cites
- 2058US12453160B2Deep etch processing for transistors having varying pitchINTEL CORP·Filed 2022·Granted Oct 21, 2025·0 cites·20 claims
- 2157US12484207B2SRAM with channel count contrast for greater read stabilityINTEL CORP·Filed 2021·Granted Nov 25, 2025·0 cites·17 claims
- 2257US2022399333A1Integrated circuit structures having metal gates with reduced aspect ratio cutsINTEL CORP·Filed 2021·Application pending·0 cites
- 2356US12507449B2Gate-all-around integrated circuit structures having necked featureINTEL CORP·Filed 2022·Granted Dec 23, 2025·0 cites·20 claims
- 2455US2022416041A1Nanoribbon subfin isolation by backside silicon substrate removal with epi protectionINTEL CORP·Filed 2021·Application pending·0 cites
- 2555US2025006808A1Integrated circuit structures with internal spacer linersINTEL CORP·Filed 2023·Application pending·0 cites
- 2655US2022406778A1Integrated circuit structures having plugged metal gatesINTEL CORP·Filed 2021·Application pending·0 cites
- 2755US2025267886A1Integrated circuit structures with void-free internal spacersINTEL CORP·Filed 2024·Application pending·0 cites
- 2854US12457778B2Conductive contacts wrapped around epitaxial source or drain regionsINTEL CORP·Filed 2022·Granted Oct 28, 2025·0 cites·20 claims
- 2953US12457779B2Gate cut structuresINTEL CORP·Filed 2022·Granted Oct 28, 2025·0 cites·20 claims
- 3052US2025204029A1Integrated circuit structure with varied sub-fin trenches and epitaxial source or drain structuresINTEL CORP·Filed 2023·Application pending·0 cites
- 3152US2025006737A1Stacked cmos transistor structures with complementary channel materialsINTEL CORP·Filed 2023·Application pending·0 cites
- 3252US2023197713A1Gate-all-around integrated circuit structures having raised wall structures for epitaxial source or drain region confinementINTEL CORP·Filed 2021·Application pending·0 cites
- 3351US2025006547A1Integrated circuit structures with removed sub-finINTEL CORP·Filed 2023·Application pending·0 cites
- 3450US2024113116A1Epitaxial structure and gate metal structures with a planar top surfaceINTEL CORP·Filed 2022·Application pending·0 cites
- 3550US2023197838A1Gate-all-around integrated circuit structures having source or drain-last structuresHASAN MOHAMMAD·Filed 2021·Application pending·0 cites
- 3649US2023207623A1Epi barrier aligned backside contactINTEL CORP·Filed 2021·Application pending·0 cites
- 3749US2023084182A1Selective depopulation of gate-all-around semiconductor devicesINTEL CORP·Filed 2021·Application pending·0 cites
- 3848US2023317789A1Source or drain structures with selective silicide contacts thereonINTEL CORP·Filed 2022·Application pending·0 cites
- 3948US2023207655A1Formation of metal contacts to silicon germanium layers with etch resistive cap layersINTEL CORP·Filed 2021·Application pending·0 cites
- 4048US2023079586A1Selectively thinned gate-all-around (gaa) structuresINTEL CORP·Filed 2021·Application pending·0 cites
- 4148US2023095191A1Transistors with reduced epitaxial source/drain span via etch-back for improved cell scalingINTEL CORP·Filed 2021·Application pending·0 cites
- 4248US2023197818A1Formation of cavity spacer and source-drain epitaxial growth for scaling of gate-all-around transistorsINTEL CORP·Filed 2021·Application pending·0 cites
- 4348US2023197816A1Integrated circuit structures having metal gate plug landed on dielectric anchorHASAN MOHAMMAD·Filed 2021·Application pending·0 cites
- 4447US2022399445A1Conductive via bar self-aligned to gate endINTEL CORP·Filed 2021·Application pending·0 cites
- 4545US2023207696A1Integrated circuits with gate plugs to induce compressive channel strainHASAN MOHAMMAD·Filed 2021·Application pending·0 cites
- 4645US2022390990A1Spacer self-aligned via structures for gate contact or trench contactINTEL CORP·Filed 2021·Application pending·0 cites
- 4744US2023207651A1Gate-all-around integrated circuit structures having source or drain structures with substrate connection portionsHASAN MOHAMMAD·Filed 2021·Application pending·0 cites
- 4842US2022415791A1Metal line profile shaping for advanced integrated circuit structure fabricationINTEL CORP·Filed 2021·Application pending·0 cites
- 4940US2024105774A1Integrated circuit structures with uniform epitaxial source or drain cutINTEL CORP·Filed 2022·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →