Inventor · disambiguated record
Mu-Jing Li
Also filed as: LI MU · LI MU-JING
32 granted patents·703 citations·filing 1999–2022
98Inventor score
Top patents by PatentIndex Score
32 records- 0193US9569517B1Fault tolerant distributed key-value storageGOOGLE INC·Filed 2013·Granted Feb 14, 2017·39 cites·16 claims
- 0293US6323614B1System and method for controlling suspension using a magnetic fieldTEXAS A & M UNIV SYS·Filed 1999·Granted Nov 27, 2001·110 cites·25 claims
- 0392US11526606B1Configuring machine learning model thresholds in models using imbalanced data setsINTUIT INC·Filed 2022·Granted Dec 13, 2022·3 cites·19 claims
- 0490US7380227B1Automated correction of asymmetric enclosure rule violations in a design layoutSUN MICROSYSTEMS INC·Filed 2005·Granted May 27, 2008·24 cites·16 claims
- 0589US6637013B1Method and system for automating design rule check error correction in a CAD environmentSUN MICROSYSTEMS INC·Filed 2000·Granted Oct 21, 2003·61 cites·7 claims
- 0688US7007258B2Method, apparatus, and computer program product for generation of a via array within a fill area of a design layoutSUN MICROSYSTEMS INC·Filed 2003·Granted Feb 28, 2006·52 cites·39 claims
- 0785US8984449B1Dynamically generating jog patches for jog violationsORACLE INT CORP·Filed 2013·Granted Mar 17, 2015·8 cites·20 claims
- 0885US7096447B1Method and apparatus for efficiently locating and automatically correcting certain violations in a complex existing circuit layoutSUN MICROSYSTEMS INC·Filed 2003·Granted Aug 22, 2006·52 cites·43 claims
- 0983US6915252B1Method and system for ensuring consistency of design rule application in a CAD environmentSUN MICROSYSTEMS INC·Filed 2000·Granted Jul 5, 2005·38 cites·11 claims
- 1083US6804808B2Redundant via rule check in a multi-wide object class design layoutSUN MICROSYSTEMS INC·Filed 2002·Granted Oct 12, 2004·37 cites·46 claims
- 1179US6892368B2Patching technique for correction of minimum area and jog design rule violationsSUN MICROSYSTEMS INC·Filed 2003·Granted May 10, 2005·26 cites·53 claims
- 1278US7519929B2Method and computer program product for interlayer connection of arbitrarily complex shapes under asymmetric via enclosure rulesSUN MICROSYSTEMS INC·Filed 2006·Granted Apr 14, 2009·8 cites·20 claims
- 1378US6718527B2Automated design rule violation correction when adding dummy geometries to a design layoutSUN MICROSYSTEMS INC·Filed 2002·Granted Apr 6, 2004·25 cites·44 claims
- 1478US6499135B1Computer aided design flow to locate grounded fill in a large scale integrated circuitSUN MICROSYSTEMS INC·Filed 2000·Granted Dec 24, 2002·32 cites·9 claims
- 1576US8117581B1Self-propelling decoupling capacitor design for flexible area decoupling capacitor fill design flowLI MU-JING·Filed 2006·Granted Feb 14, 2012·7 cites·8 claims
- 1676US6883149B2Via enclosure rule check in a multi-wide object class design layoutSUN MICROSYSTEMS INC·Filed 2002·Granted Apr 19, 2005·23 cites·42 claims
- 1775US6832360B2Pure fill via area extraction in a multi-wide object class design layoutSUN MICROSYSTEMS INC·Filed 2002·Granted Dec 14, 2004·20 cites·32 claims
- 1875US6735749B2(Design rule check)/(electrical rule check) algorithms using a system resolutionSUN MICROSYSTEMS INC·Filed 2002·Granted May 11, 2004·21 cites·12 claims
- 1973US8645453B2Method and system of processing cookies across domainsCHENG LIMIN·Filed 2010·Granted Feb 4, 2014·9 cites·20 claims
- 2070US6892363B2Correction of width violations of dummy geometriesSUN MICROSYSTEMS INC·Filed 2002·Granted May 10, 2005·14 cites·32 claims
- 2170US6871332B2Structure and method for separating geometries in a design layout into multi-wide object classesSUN MICROSYSTEMS INC·Filed 2002·Granted Mar 22, 2005·15 cites·53 claims
- 2269US9230049B1Arraying power grid vias by tile cellsORACLE INT CORP·Filed 2014·Granted Jan 5, 2016·2 cites·20 claims
- 2369US6895568B2Correction of spacing violations between pure fill via areas in a multi-wide object class design layoutSUN MICROSYSTEMS INC·Filed 2002·Granted May 17, 2005·13 cites·48 claims
- 2469US6775806B2Method, system and computer product to produce a computer-generated integrated circuit designSUN MICROSYSTEMS INC·Filed 2002·Granted Aug 10, 2004·14 cites·20 claims
- 2566US8891878B2Method for representing images using quantized embeddings of scale-invariant image featuresRANE SHANTANU·Filed 2012·Granted Nov 18, 2014·3 cites·18 claims
- 2665US6769099B2Method to simplify and speed up design rule/electrical rule checksSUN MICROSYSTEMS INC·Filed 2002·Granted Jul 27, 2004·11 cites·20 claims
- 2765US6608335B2Grounded fill in a large scale integrated circuitSUN MICROSYSTEMS INC·Filed 2000·Granted Aug 19, 2003·14 cites·18 claims
- 2862US8423943B2Self-propelling decoupling capacitor design for flexible area decoupling capacitor fill design flowLI MU-JING·Filed 2012·Granted Apr 16, 2013·1 cites·13 claims
- 2962US6816998B2Correction of spacing violations between dummy geometries and wide class objects of design geometriesSUN MICROSYSTEMS INC·Filed 2002·Granted Nov 9, 2004·8 cites·40 claims
- 3060US6792586B2Correction of spacing violations between wide class objects of dummy geometriesSUN MICROSYSTEMS INC·Filed 2002·Granted Sep 14, 2004·7 cites·42 claims
- 3159US8719756B2Power grid mosaicing with deep-sub-tile cellsLI MU-JING·Filed 2011·Granted May 6, 2014·1 cites·20 claims
- 3257US6772401B2Correction of spacing violations between design geometries and wide class objects of dummy geometriesSUN MICROSYSTEMS INC·Filed 2002·Granted Aug 3, 2004·5 cites·35 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →