Inventor · disambiguated record
Nagi Aboulenein
Also filed as: ABOULENEIN NAGI
23 granted patents·4 pending applications·341 citations·filing 2001–2025
94Inventor score
Top patents by PatentIndex Score
27 records- 0197US12204410B2Integrated error correction code (ECC) and parity protection in memory control circuits for increased memory utilizationAMPERE COMPUTING LLC·Filed 2022·Granted Jan 21, 2025·14 cites·25 claims
- 0295US6792496B2Prefetching data for peripheral component interconnect devicesINTEL CORP·Filed 2001·Granted Sep 14, 2004·134 cites·39 claims
- 0392US8443151B2Prefetch optimization in shared resource multi-core systemsTANG PUQI P·Filed 2009·Granted May 14, 2013·51 cites·38 claims
- 0491US10482947B2Integrated error checking and correction (ECC) in byte mode memory devicesINTEL CORP·Filed 2018·Granted Nov 19, 2019·7 cites·21 claims
- 0589US9851771B2Dynamic power measurement and estimation to improve memory subsystem power performanceINTEL CORP·Filed 2013·Granted Dec 26, 2017·18 cites·21 claims
- 0686US11934263B2Parity protected memory blocks merged with error correction code (ECC) protected blocks in a codeword for increased memory utilizationAMPERE COMPUTING LLC·Filed 2022·Granted Mar 19, 2024·1 cites·24 claims
- 0786US9940984B1Shared command address (C/A) bus for multiple memory channelsINTEL CORP·Filed 2016·Granted Apr 10, 2018·8 cites·21 claims
- 0886US6785793B2Method and apparatus for memory access scheduling to reduce memory access latencyINTEL CORP·Filed 2001·Granted Aug 31, 2004·60 cites·56 claims
- 0984US8924651B2Prefetch optimization in shared resource multi-core systemsINTEL CORP·Filed 2013·Granted Dec 30, 2014·9 cites·20 claims
- 1079US7127574B2Method and apparatus for out of order memory schedulingINTEL CORPORATIOON·Filed 2003·Granted Oct 24, 2006·34 cites·42 claims
- 1178US2025231236A1Component die validation built-in self-test (vbist) engineAMPERE COMPUTING LLC·Filed 2025·Application pending·0 cites
- 1275US12314130B2Parity protected memory blocks merged with error correction code (ECC) protected blocks in a codeword for increased memory utilizationAMPERE COMPUTING LLC·Filed 2024·Granted May 27, 2025·0 cites·17 claims
- 1372US9722663B2Interference testingINTEL CORP·Filed 2014·Granted Aug 1, 2017·3 cites·9 claims
- 1471US12282064B2Component die validation built-in self-test (VBIST) engineAMPERE COMPUTING LLC·Filed 2022·Granted Apr 22, 2025·0 cites·35 claims
- 1567US12474848B2Techniques for memory resource control using memory resource partitioning and monitoringAMPERE COMPUTING LLC·Filed 2023·Granted Nov 18, 2025·0 cites·20 claims
- 1664US9514047B2Apparatus and method to dynamically expand associativity of a cache memoryINTEL CORP·Filed 2014·Granted Dec 6, 2016·1 cites·20 claims
- 1759US11586537B2Method, apparatus, and system for run-time checking of memory tags in a processor-based systemAMPERE COMPUTING LLC·Filed 2021·Granted Feb 21, 2023·0 cites·33 claims
- 1859US10516439B2Interference testingINTEL CORP·Filed 2017·Granted Dec 24, 2019·0 cites·9 claims
- 1955US12159056B2Extending functionality of memory controllers in a processor-based deviceAMPERE COMPUTING LLC·Filed 2022·Granted Dec 3, 2024·0 cites·19 claims
- 2054US8683096B2Configuration of data strobesHOSSAIN MD ALTAF·Filed 2012·Granted Mar 25, 2014·1 cites·22 claims
- 2151US12451206B2Extending functionality of memory controllers using a loopback mode for testing in a processor-based deviceAMPERE COMPUTING LLC·Filed 2023·Granted Oct 21, 2025·0 cites·20 claims
- 2250US10621094B2Coarse tag replacementINTEL CORP·Filed 2017·Granted Apr 14, 2020·0 cites·16 claims
- 2348US12182417B2Address-range memory mirroring in a computer system, and related methodsAMPERE COMPUTING LLC·Filed 2022·Granted Dec 31, 2024·0 cites·19 claims
- 2445US9268724B2Configuration of data strobesINTEL CORP·Filed 2014·Granted Feb 23, 2016·0 cites·23 claims
- 2542US2019102314A1Tag cache adaptive power gatingINTEL CORP·Filed 2017·Application pending·0 cites
- 2638US2008162799A1Mechanism for write optimization to a memory deviceSPRY BRYAN·Filed 2006·Application pending·0 cites
- 2737US2019332469A1Address range based in-band memory error-correcting code protection module with syndrome bufferINTEL CORP·Filed 2019·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →