Inventor · disambiguated record
Nathan C. Buck
Also filed as: BUCK NATHAN · BUCK NATHAN C
33 granted patents·5 pending applications·197 citations·filing 2007–2023
97Inventor score
Top patents by PatentIndex Score
38 records- 0194US9767239B1Timing optimization driven by statistical sensitivitesIBM·Filed 2016·Granted Sep 19, 2017·13 cites·22 claims
- 0292US9519747B1Dynamic and adaptive timing sensitivity during static timing analysis using look-up tableGLOBALFOUNDRIES INC·Filed 2015·Granted Dec 13, 2016·10 cites·20 claims
- 0392US9495497B1Dynamic voltage frequency scalingIBM·Filed 2015·Granted Nov 15, 2016·10 cites·20 claims
- 0490US7555740B2Method and system for evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysisIBM·Filed 2007·Granted Jun 30, 2009·25 cites·22 claims
- 0588US10346569B2Multi-sided variations for creating integrated circuitsIBM·Filed 2017·Granted Jul 9, 2019·4 cites·1 claims
- 0687US8141012B2Timing closure on multiple selective corners in a single statistical timing runBUCK NATHAN C·Filed 2009·Granted Mar 20, 2012·18 cites·22 claims
- 0785US8769452B2Parasitic extraction in an integrated circuit with multi-patterning requirementsIBM·Filed 2012·Granted Jul 1, 2014·7 cites·10 claims
- 0885US8468483B2Method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependenceBUCK NATHAN C·Filed 2011·Granted Jun 18, 2013·9 cites·20 claims
- 0985US7784003B2Estimation of process variation impact of slack in multi-corner path-based static timing analysisIBM·Filed 2007·Granted Aug 24, 2010·17 cites·20 claims
- 1084US8949765B2Modeling multi-patterning variability with statistical timingIBM·Filed 2013·Granted Feb 3, 2015·5 cites·7 claims
- 1183US8850378B2Hierarchical design of integrated circuits with multi-patterning requirementsIBM·Filed 2012·Granted Sep 30, 2014·6 cites·12 claims
- 1280US8806402B2Modeling multi-patterning variability with statistical timingIBM·Filed 2012·Granted Aug 12, 2014·4 cites·11 claims
- 1379US8560989B2Statistical clock cycle computationBUCK NATHAN·Filed 2011·Granted Oct 15, 2013·6 cites·20 claims
- 1479US7681157B2Variable threshold system and method for multi-corner static timing analysisIBM·Filed 2007·Granted Mar 16, 2010·10 cites·15 claims
- 1578US7873926B2Methods for practical worst test definition and debug during block based statistical static timing analysisIBM·Filed 2008·Granted Jan 18, 2011·9 cites·2 claims
- 1677US8768679B2System and method for efficient modeling of NPskew effects on static timing testsBUCK NATHAN C·Filed 2010·Granted Jul 1, 2014·5 cites·21 claims
- 1776US7886246B2Methods for identifying failing timing requirements in a digital designIBM·Filed 2008·Granted Feb 8, 2011·7 cites·10 claims
- 1874US9378328B2Modeling multi-patterning variability with statistical timingIBM·Filed 2014·Granted Jun 28, 2016·2 cites·10 claims
- 1974US8086988B2Chip design and fabrication method optimized for profitBUCK NATHAN·Filed 2009·Granted Dec 27, 2011·7 cites·25 claims
- 2072US9348962B2Hierarchical design of integrated circuits with multi-patterning requirementsIBM·Filed 2014·Granted May 24, 2016·2 cites·13 claims
- 2172US8056035B2Method and system for analyzing cross-talk coupling noise events in block-based statistical static timingIBM·Filed 2008·Granted Nov 8, 2011·5 cites·20 claims
- 2271US9858368B2Integrating manufacturing feedback into integrated circuit structure designBUCK NATHAN C·Filed 2011·Granted Jan 2, 2018·3 cites·14 claims
- 2370US7844932B2Method to identify timing violations outside of manufacturing specification limitsIBM·Filed 2008·Granted Nov 30, 2010·4 cites·5 claims
- 2468US10891412B1Offline analysis of hierarchical electronic design automation derived dataIBM·Filed 2020·Granted Jan 12, 2021·1 cites·20 claims
- 2565US9171124B2Parasitic extraction in an integrated circuit with multi-patterning requirementsIBM·Filed 2013·Granted Oct 27, 2015·1 cites·12 claims
- 2665US8656207B2Method for modeling variation in a feedback loop of a phase-locked loopBUCK NATHAN C·Filed 2009·Granted Feb 18, 2014·5 cites·18 claims
- 2761US7797657B2Parameter ordering for multi-corner static timing analysisIBM·Filed 2007·Granted Sep 14, 2010·2 cites·16 claims
- 2860US10380289B2Multi-sided variations for creating integrated circuitsIBM·Filed 2017·Granted Aug 13, 2019·0 cites·9 claims
- 2958US10380286B2Multi-sided variations for creating integrated circuitsIBM·Filed 2017·Granted Aug 13, 2019·0 cites·11 claims
- 3057US10289776B2Sensitivity calculation filtering for statistical static timing analysis of an integrated circuitIBM·Filed 2018·Granted May 14, 2019·0 cites·15 claims
- 3155US10489540B2Integrating manufacturing feedback into integrated circuit structure designIBM·Filed 2017·Granted Nov 26, 2019·0 cites·18 claims
- 3253US2024386175A1Timing analysis for non-scan latchesIBM·Filed 2023·Application pending·0 cites
- 3353US2025005244A1Timing constraint auto-creation for integrated circuit testingIBM·Filed 2023·Application pending·0 cites
- 3452US10031985B2Sensitivity calculation filtering for statistical static timing analysis of an integrated circuitIBM·Filed 2016·Granted Jul 24, 2018·0 cites·13 claims
- 3547US2009210839A1Timing closure using multiple timing runs which distribute the frequency of identified fails per timing cornerIBM·Filed 2008·Application pending·0 cites
- 3642US10372851B2Independently projecting a canonical clockIBM·Filed 2017·Granted Aug 6, 2019·0 cites·17 claims
- 3741US2015073738A1Determining process variation using device threshold sensitivitesIBM·Filed 2013·Application pending·0 cites
- 3841US2019362043A1Dynamic update of macro timing models during higher-level timing analysisIBM·Filed 2018·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →