Inventor · disambiguated record
Navneet Kaushik
Also filed as: KAUSHIK NAVNEET
6 granted patents·38 citations·filing 2012–2016
81Inventor score
Top patents by PatentIndex Score
6 records- 0190US9640280B1Power domain aware insertion methods and designs for testing and repairing memoryCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted May 2, 2017·8 cites·20 claims
- 0287US9865362B1Method and apparatus for testing error correction code (ECC) logic and physical memory onboard a manufactured integrated circuit (IC)CADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jan 9, 2018·9 cites·20 claims
- 0384US10095822B1Memory built-in self-test logic in an integrated circuit designCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Oct 9, 2018·4 cites·20 claims
- 0483US10192013B1Test logic at register transfer level in an integrated circuit designCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jan 29, 2019·5 cites·20 claims
- 0579US8719761B2Method and apparatus for optimizing memory-built-in-self testCARD NORMAN·Filed 2012·Granted May 6, 2014·8 cites·44 claims
- 0673US8990749B2Method and apparatus for optimizing memory-built-in-self testARORA PUNEET·Filed 2012·Granted Mar 24, 2015·4 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →