Inventor · disambiguated record
Narasimha Lanka
Also filed as: LANKA NARASIMHA · LANKA NARASIMHA R
20 granted patents·7 pending applications·23 citations·filing 2014–2023
90Inventor score
Top patents by PatentIndex Score
27 records- 0193US12360934B2Parameter exchange for a die-to-die interconnectINTEL CORP·Filed 2022·Granted Jul 15, 2025·2 cites·20 claims
- 0292US9692402B2Method, apparatus, system for centering in a high performance interconnectINTEL CORP·Filed 2014·Granted Jun 27, 2017·10 cites·23 claims
- 0391US12332826B2Die-to-die interconnectINTEL CORP·Filed 2022·Granted Jun 17, 2025·2 cites·20 claims
- 0488US11599497B2High performance interconnectINTEL CORP·Filed 2020·Granted Mar 7, 2023·2 cites·22 claims
- 0587US12481614B2Standard interfaces for die to die (D2D) interconnect stacksINTEL CORP·Filed 2022·Granted Nov 25, 2025·1 cites·20 claims
- 0687US12353305B2Compliance and debug testing of a die-to-die interconnectINTEL CORP·Filed 2022·Granted Jul 8, 2025·1 cites·20 claims
- 0780US12181966B2Reduction of latency impact of on-die error checking and correction (ECC)INTEL CORP·Filed 2021·Granted Dec 31, 2024·1 cites·18 claims
- 0880US10789201B2High performance interconnectINTEL CORP·Filed 2017·Granted Sep 29, 2020·3 cites·19 claims
- 0977US12117960B2Approximate data bus inversion technique for latency sensitive applicationsINTEL CORP·Filed 2020·Granted Oct 15, 2024·1 cites·20 claims
- 1069US12505065B2On-package die-to-die (D2D) interconnect for memory using universal chiplet interconnect express (UCIe) PHYINTEL CORP·Filed 2023·Granted Dec 23, 2025·0 cites·20 claims
- 1163US11971841B2Link layer-PHY interface adapterINTEL CORP·Filed 2020·Granted Apr 30, 2024·0 cites·20 claims
- 1261US12499019B2Retimers to extend a die-to-die interconnectINTEL CORP·Filed 2022·Granted Dec 16, 2025·0 cites·20 claims
- 1360US12362306B2Clock-gating in die-to-die (D2D) interconnectsINTEL CORP·Filed 2022·Granted Jul 15, 2025·0 cites·20 claims
- 1458US12468597B2Valid signal for latency sensitive die-to-die (D2D) interconnectsINTEL CORP·Filed 2022·Granted Nov 11, 2025·0 cites·21 claims
- 1557US10560081B2Method, apparatus, system for centering in a high performance interconnectINTEL CORP·Filed 2017·Granted Feb 11, 2020·0 cites·21 claims
- 1656US12321305B2Sideband interface for die-to-die interconnectsINTEL CORP·Filed 2022·Granted Jun 3, 2025·0 cites·20 claims
- 1754US12405912B2Link initialization training and bring up for die-to-die interconnectINTEL CORP·Filed 2022·Granted Sep 2, 2025·0 cites·20 claims
- 1854US2023258716A1Techniques to perform semiconductor testingINTEL CORP·Filed 2023·Application pending·0 cites
- 1953US12316343B2PHY-based retry techniques for die-to-die interfacesINTEL CORP·Filed 2021·Granted May 27, 2025·0 cites·23 claims
- 2052US12347818B2Logic die in a multi-chip package having a configurable physical interface to on-package memoryINTEL CORP·Filed 2021·Granted Jul 1, 2025·0 cites·18 claims
- 2152US2022327084A1Die-to-die interconnect protocol layerINTEL CORP·Filed 2022·Application pending·0 cites
- 2251US11954360B2Technology to provide accurate training and per-bit deskew capability for high bandwidth memory input/output linksINTEL CORP·Filed 2020·Granted Apr 9, 2024·0 cites·20 claims
- 2351US2023230923A1Microelectronic die including swappable phy circuitry and semiconductor package including sameINTEL CORP·Filed 2022·Application pending·0 cites
- 2448US2022342841A1Die-to-die adapterCHOUDHARY SWADESH·Filed 2022·Application pending·0 cites
- 2545US2022271912A1Clock phase management for die-to-die (d2d) interconnectPASDAST GERALD·Filed 2022·Application pending·0 cites
- 2644US2020251159A1Stacked memory device with end to end data bus inversionINTEL CORP·Filed 2020·Application pending·0 cites
- 2741US2022011795A1Control Apparatus, Device, Method and Computer Program for Determining a Device-Specific Supply Voltage for a Semiconductor DeviceINTEL CORP·Filed 2021·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →