Logic die in a multi-chip package having a configurable physical interface to on-package memory

Abstract

A multi-chip device having a configurable physical interface in a logic die to on-package memory is provided. The configurable physical interface to allow a connection from a signal on the memory interface to be selected based on whether the logic die is mirrored or non-mirrored.

What is claimed is: 
     
       1. A multi-chip device comprising:
 a memory die; 
 a logic die including a memory controller and a memory interface to connections between the memory die and the logic die; 
 a mirrored logic die mirrored along a mirror plane of the logic die, the connections mismatched between the memory die and the mirrored logic die; 
 the memory interface to configure the connections between the memory die and the logic die, including to configure mismatched connections between the memory die and the mirrored logic die, using a channel mapping to map a memory die channel bump matrix to respective logic die and mirrored logic die channel bump matrices; and 
 the memory controller to route channel signals transmitted on channel bumps between the memory die and the respective logic die and mirrored logic die based on the configured connections and configured mismatched connections. 
 
     
     
       2. The multi-chip device of  claim 1 , wherein the memory die is a High Bandwidth Memory die and the logic die is a System on Chip die. 
     
     
       3. The multi-chip device of  claim 1 , wherein a channel order in a channel bump matrix on the mirrored logic die and the channel order in a channel bump matrix on the memory die are different resulting in one or more of the mismatched connections. 
     
     
       4. The multi-chip device of  claim 1 , wherein the channel signals include pseudo channel signals, further comprising:
 the memory interface to configure the connections and the mismatched connections using a pseudo channel mapping to map pseudo channels in the memory die channel bump matrix to corresponding pseudo channels in the respective logic die and mirrored logic die channel bump matrices; and 
 the memory controller to route the pseudo channel signals transmitted on channel bumps between the memory die and the respective logic die and mirrored logic die based on the configured connections and configured mismatched connections. 
 
     
     
       5. The multi-chip device of  claim 1 , further comprising a bridge. 
     
     
       6. The multi-chip device of  claim 1 , further comprising an interposer. 
     
     
       7. A system comprising:
 a processor; and 
 a multi-chip device comprising: 
 a memory die, 
 a logic die including a memory controller and a memory interface to connections between the memory die and the logic die, 
 a mirrored logic die mirrored along a mirror plane of the logic die, the connections mismatched between the memory die and the mirrored logic die, 
 the memory interface to configure the connections between the memory die and the logic die, including to configure mismatched connections between the memory die and the mirrored logic die, using a channel mapping to map a memory die channel bump matrix to respective logic die and mirrored logic die channel bump matrices, and 
 the memory controller to route channel signals transmitted on channel bumps between the memory die and the respective logic die and mirrored logic die based on the configured connections and configured mismatched connections. 
 
     
     
       8. The system of  claim 7 , wherein the memory die is a High Bandwidth Memory die and the logic die is a System on Chip die. 
     
     
       9. The system of  claim 7 , wherein a channel order in a channel bump matrix on the mirrored logic die and the channel order in a channel bump matrix on the memory die are different resulting in one or more of the mismatched connections. 
     
     
       10. The system of  claim 7 , wherein the channel signals include pseudo channel signals, further comprising:
 the memory interface to configure the connections and the mismatched connections using a pseudo channel mapping to map pseudo channels in the memory die channel bump matrix to corresponding pseudo channels in the respective logic die and mirrored logic die channel bump matrices; and 
 the memory controller to route the pseudo channel signals transmitted on channel bumps between the memory die and the respective logic die and mirrored logic die based on the configured connections and configured mismatched connections. 
 
     
     
       11. The system of  claim 7 , wherein the multi-chip device further comprising a bridge. 
     
     
       12. The system of  claim 7 , wherein the multi-chip device further comprising an interposer. 
     
     
       13. The system of  claim 7 , further comprising one or more of:
 a display communicatively coupled to the processor; or 
 a battery coupled to the processor. 
 
     
     
       14. A method comprising:
 in a multi-chip device including: 
 a memory die and a logic die, the logic die including a memory controller and a memory interface to connections between the memory die and the logic die, and 
 a mirrored logic die mirrored along a mirror plane of the logic die, the connections mismatched between the memory die and the mirrored logic die; 
 the memory interface configuring the connections between the memory die and the logic die and mismatched connections between the memory die and the mirrored logic die, including mapping a memory die channel bump matrix to respective logic die and mirrored logic die channel bump matrices using a channel mapping; and 
 the memory controller routing channel signals transmitted on channel bumps between the memory die and the respective logic die and mirrored logic die according to the configured connections and configured mismatched connections. 
 
     
     
       15. The method of  claim 14 , wherein the memory die is a High Bandwidth Memory die and the logic die is a System on Chip die. 
     
     
       16. The method of  claim 14 , wherein a channel order in a channel bump matrix on the mirrored logic die and the channel order in a channel bump matrix on the memory die are different resulting in one or more of the mismatched connections. 
     
     
       17. The method of  claim 14 , wherein the channel signals include pseudo channel signals, further comprising:
 the memory interface configuring the connections and the mismatched connections, including mapping pseudo channels in the memory die channel bump matrix to corresponding pseudo channels in the respective logic die and mirrored logic die channel bump matrices using a pseudo channel mapping; and 
 the memory controller routing the pseudo channel signals transmitted on channel bumps between the memory die and the respective logic die and mirrored logic die according to the configured connections and configured mismatched connections. 
 
     
     
       18. The method of  claim 14 , wherein the multi-chip device further comprises any of a bridge and an interposer.