Inventor · disambiguated record
Nanju Na
Also filed as: NA NANJU
15 granted patents·6 pending applications·20 citations·filing 2007–2017
88Inventor score
Top patents by PatentIndex Score
21 records- 0177US8110500B2Mitigation of plating stub resonance by controlling surface roughnessMUTNURY BHYRAV M·Filed 2008·Granted Feb 7, 2012·6 cites·7 claims
- 0276US9548808B2Dynamic optical channel sparing in an industry standard input/output subsystemIBM·Filed 2014·Granted Jan 17, 2017·4 cites·13 claims
- 0375US8569873B2Mitigation of plating stub resonance by controlling surface roughnessMUTNURY BHYRAV M·Filed 2011·Granted Oct 29, 2013·3 cites·14 claims
- 0472US9705591B2Dynamic optical channel sparing in an industry standard input/output subsystemIBM·Filed 2015·Granted Jul 11, 2017·2 cites·10 claims
- 0565US8402406B2Controlling plating stub reflections in a chip packageCASES MOISES·Filed 2010·Granted Mar 19, 2013·2 cites·11 claims
- 0663US10620253B2Noise modulation for on-chip noise measurementIBM·Filed 2017·Granted Apr 14, 2020·0 cites·20 claims
- 0757US9835665B2Noise modulation for on-chip noise measurementIBM·Filed 2014·Granted Dec 5, 2017·0 cites·11 claims
- 0857US9797938B2Noise modulation for on-chip noise measurementIBM·Filed 2014·Granted Oct 24, 2017·0 cites·14 claims
- 0954US9118144B2Multi-level connector and use thereof that mitigates data signaling reflectionsHASSE MICHAEL D·Filed 2012·Granted Aug 25, 2015·3 cites·19 claims
- 1053US8830690B2Minimizing plating stub reflections in a chip package using capacitanceMUTNURY BHYRAV M·Filed 2008·Granted Sep 9, 2014·0 cites·14 claims
- 1152US2014284217A1Minimizing plating stub reflections in a chip package using capacitanceIBM·Filed 2014·Application pending·0 cites
- 1252US2014167886A1Plating Stub Resonance Shift with Filter Stub Design MethodologyIBM·Filed 2013·Application pending·0 cites
- 1350US8102042B2Reducing plating stub reflections in a chip package using resistive couplingCASES MOISES·Filed 2009·Granted Jan 24, 2012·0 cites·14 claims
- 1449US9838110B2Dynamic link repair from lane failure with minimal link-down time while sparing fault channelsIBM·Filed 2015·Granted Dec 5, 2017·0 cites·6 claims
- 1549US9774389B2Dynamic link repair from lane failure with minimal link down-time while sparing fault channelsIBM·Filed 2015·Granted Sep 26, 2017·0 cites·9 claims
- 1649US2013328645A1Plating Stub Resonance Shift with Filter Stub Design MethodologyNA NANJU·Filed 2012·Application pending·0 cites
- 1748US2011103030A1Packages and Methods for Mitigating Plating Stub EffectsIBM·Filed 2009·Application pending·0 cites
- 1846US9253874B2Printed circuit board having DC blocking dielectric waveguide viasIBM·Filed 2012·Granted Feb 2, 2016·0 cites·10 claims
- 1945US2011061898A1Reducing cross-talk in high speed ceramic packages using selectively-widened meshIBM·Filed 2009·Application pending·0 cites
- 2043US9209583B2Multi-level connector and use thereof that mitigates data signaling reflectionsIBM·Filed 2013·Granted Dec 8, 2015·0 cites·2 claims
- 2140US2009085155A1Method and apparatus for package-to-board impedance matching for high speed integrated circuitsBAILEY MARK J·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →