Minimizing plating stub reflections in a chip package using capacitance

Abstract

The present invention is directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a method including capacitively coupling a plating stub to ground so that the resonant frequency caused by the plating stub in a semiconductor package is shifted away from an operational frequency.

What is claimed is: 
     
         1 . A method, comprising:
 capacitively coupling a plating stub to ground so that the resonant frequency caused by the plating stub in a semiconductor package is shifted away from an operational frequency.   
     
     
         2 . The method of  claim 1 , further comprising:
 forming the plating stub by electroplating a portion of a substrate along an electrical pathway extending from a periphery of the substrate to the portion of the substrate being electroplated.   
     
     
         3 . The method of  claim 1 , wherein capacitively coupling the plating stub to ground includes connecting a first lead of a capacitor to the plating stub and a second lead of the capacitor to ground. 
     
     
         4 . The method of  claim 1 , wherein capacitively coupling the plating stub to ground includes forming an embedded capacitor in the substrate that couples the plating stub in an outer layer to a ground layer spaced from the outer layer. 
     
     
         5 . The method of  claim 1 , wherein the semiconductor package includes a ground layer and a first outer layer, wherein the first outer layer provides a chip mounting location, a signal interconnect spaced from the chip mounting location, a signal trace extending from near the chip mounting location to the signal interconnect, and the plating stub, wherein the plating stub extends from the signal interconnect.