Inventor · disambiguated record
Natarajan Viswanathan
Also filed as: VISWANATHAN NATARAJAN
40 granted patents·3 pending applications·327 citations·filing 2005–2023
97Inventor score
Files withIBM11CADENCE DESIGN SYSTEMS INC10ALPERT CHARLES J9ALPERT CHARLES JAY2JOHARAPURKAR ASHUTOSH RAVINDRA2
Top patents by PatentIndex Score
43 records- 0196US11645441B1Machine-learning based clustering for clock tree synthesisCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted May 9, 2023·12 cites·20 claims
- 0296US10963617B1Modifying route topology to fix clock tree violationsCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Mar 30, 2021·11 cites·20 claims
- 0396US8830207B1Method and apparatus for improving dynamic range of a touchscreen controllerMAXIM INTEGRATED PRODUCTS·Filed 2013·Granted Sep 9, 2014·20 cites·10 claims
- 0493US11244099B1Machine-learning based prediction method for iterative clustering during clock tree synthesisCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Feb 8, 2022·4 cites·18 claims
- 0593US8677299B1Latch clustering with proximity to local clock buffersIBM·Filed 2013·Granted Mar 18, 2014·22 cites·17 claims
- 0692US11188702B1Dynamic weighting scheme for local cluster refinementCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Nov 30, 2021·3 cites·20 claims
- 0792US8954912B2Structured placement of latches/flip-flops to minimize clock power in high-performance designsIBM·Filed 2012·Granted Feb 10, 2015·18 cites·25 claims
- 0892US8495548B2Multi-patterning lithography aware cell placement in integrated circuit designAGARWAL KANAK BEHARI·Filed 2011·Granted Jul 23, 2013·22 cites·20 claims
- 0992US8493356B2Noise cancellation technique for capacitive touchscreen controller using differential sensingJOHARAPURKAR ASHUTOSH RAVINDRA·Filed 2011·Granted Jul 23, 2013·25 cites·30 claims
- 1091US8793636B2Placement of structured netsALPERT CHARLES J·Filed 2011·Granted Jul 29, 2014·17 cites·23 claims
- 1190US8453093B2Alignment net insertion for straightening the datapath in a force-directed placerKIM MYUNG-CHUL·Filed 2011·Granted May 28, 2013·13 cites·20 claims
- 1290US7266796B1Fastplace method for integrated circuit designUNIV IOWA STATE RES FOUND INC·Filed 2005·Granted Sep 4, 2007·45 cites·15 claims
- 1388US8782584B2Post-placement cell shiftingIBM·Filed 2013·Granted Jul 15, 2014·10 cites·1 claims
- 1487US9495501B1Large cluster persistence during placement optimization of integrated circuit designsIBM·Filed 2016·Granted Nov 15, 2016·4 cites·10 claims
- 1586US8667441B2Clock optimization with local clock buffer control optimizationALPERT CHARLES J·Filed 2010·Granted Mar 4, 2014·10 cites·20 claims
- 1686US7934188B2Legalization of VLSI circuit placement with blockages using hierarchical row slicingIBM·Filed 2008·Granted Apr 26, 2011·16 cites·18 claims
- 1785US10402522B1Region aware clusteringCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Sep 3, 2019·4 cites·20 claims
- 1885US10289797B1Local cluster refinementCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted May 14, 2019·4 cites·20 claims
- 1984US9251306B2Alignment net insertion for straightening the datapath in a force-directed placerGLOBALFOUNDRIES INC·Filed 2013·Granted Feb 2, 2016·6 cites·20 claims
- 2083US8589848B2Datapath placement using tiered assignmentALPERT CHARLES J·Filed 2012·Granted Nov 19, 2013·7 cites·25 claims
- 2182US8458634B2Latch clustering with proximity to local clock buffersALPERT CHARLES JAY·Filed 2010·Granted Jun 4, 2013·7 cites·17 claims
- 2281US9098669B1Boundary latch and logic placement to satisfy timing constraintsIBM·Filed 2014·Granted Aug 4, 2015·7 cites·24 claims
- 2379US8595675B1Local objective optimization in global placement of an integrated circuit designALPERT CHARLES J·Filed 2012·Granted Nov 26, 2013·5 cites·12 claims
- 2479US8495534B2Post-placement cell shiftingALPERT CHARLES J·Filed 2010·Granted Jul 23, 2013·5 cites·23 claims
- 2578US9442610B2Noise cancellation technique for capacitive touchscreen controller using differential sensingMAXIM INTEGRATED PRODUCTS·Filed 2013·Granted Sep 13, 2016·4 cites·30 claims
- 2678US9391607B2Use of random sampling technique to reduce finger-coupled noiseJOHARAPURKAR ASHUTOSH RAVINDRA·Filed 2011·Granted Jul 12, 2016·5 cites·11 claims
- 2777US10318693B1Balanced scaled-load clusteringCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Jun 11, 2019·2 cites·20 claims
- 2877US8347257B2Detailed routability by cell placementIBM·Filed 2010·Granted Jan 1, 2013·5 cites·24 claims
- 2977US7882475B2Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectorsIBM·Filed 2008·Granted Feb 1, 2011·8 cites·3 claims
- 3075US9870097B2Noise cancellation technique for capacitive touchscreen controller using differential sensingQUALCOMM INC·Filed 2016·Granted Jan 16, 2018·2 cites·13 claims
- 3172US8418108B2Accuracy pin-slew mode for gate delay calculationALPERT CHARLES J·Filed 2011·Granted Apr 9, 2013·3 cites·15 claims
- 3263US10685160B2Large cluster persistence during placement optimization of integrated circuit designsIBM·Filed 2018·Granted Jun 16, 2020·0 cites·18 claims
- 3362US12339701B1Insertion delay and area tradeoff for buffering solution selection in clock tree synthesisCADENCE DESIGN SYSTEMS INC·Filed 2023·Granted Jun 24, 2025·0 cites·20 claims
- 3458US8347249B2Incremental timing optimization and placementIBM·Filed 2009·Granted Jan 1, 2013·1 cites·25 claims
- 3557US10140409B2Large cluster persistence during placement optimization of integrated circuit designsIBM·Filed 2016·Granted Nov 27, 2018·0 cites·5 claims
- 3656US12321193B1Hierarchically-aware buffering for clock structuresCADENCE DESIGN SYSTEMS INC·Filed 2023·Granted Jun 3, 2025·0 cites·19 claims
- 3749US9524363B2Element placement in circuit design based on preferred locationALPERT CHARLES J·Filed 2012·Granted Dec 20, 2016·0 cites·19 claims
- 3848US11625525B1Grouping cells in cell library based on clusteringCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Apr 11, 2023·0 cites·20 claims
- 3946US8769457B2Separate refinement of local wirelength and local module density in intermediate placement of an integrated circuit designALPERT CHARLES J·Filed 2012·Granted Jul 1, 2014·0 cites·18 claims
- 4046US2016291797A1Use of random sampling technique to reduce finger-coupled noiseQUALCOMM TECHNOLOGIES INC·Filed 2016·Application pending·0 cites
- 4144US2008066037A1Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectorsINTERNAT BUSINESS MACHINES COM·Filed 2006·Application pending·0 cites
- 4241US2012297355A1Whitespace creation and preservation in circuit designALPERT CHARLES JAY·Filed 2011·Application pending·0 cites
- 4337US8683411B2Electronic design automation object placement with partially region-constrained objectsALPERT CHARLES J·Filed 2010·Granted Mar 25, 2014·0 cites·25 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →