Inventor · disambiguated record
Nishu Kohli
Also filed as: KOHLI NISHU
13 granted patents·27 citations·filing 2006–2017
87Inventor score
Top patents by PatentIndex Score
13 records- 0186US9812219B2Automatic test-pattern generation for memory-shadow-logic testingST MICROELECTRONICS INT NV·Filed 2015·Granted Nov 7, 2017·3 cites·24 claims
- 0286US9003255B2Automatic test-pattern generation for memory-shadow-logic testingKOHLI NISHU·Filed 2011·Granted Apr 7, 2015·6 cites·15 claims
- 0384US8929115B2XY ternary content addressable memory (TCAM) cell and arrayKOHLI NISHU·Filed 2011·Granted Jan 6, 2015·9 cites·21 claims
- 0476US10535416B2Automatic test-pattern generation for memory-shadow-logic testingST MICROELECTRONICS INT NV·Filed 2017·Granted Jan 14, 2020·3 cites·20 claims
- 0563US8681534B2Dual port register file memory cell with reduced susceptibility to noise during same row accessKOHLI NISHU·Filed 2011·Granted Mar 25, 2014·3 cites·12 claims
- 0662US8730756B2Dual clock edge triggered memoryKOHLI NISHU·Filed 2011·Granted May 20, 2014·2 cites·28 claims
- 0757US8913457B2Dual clock edge triggered memoryST MICROELECTRONICS INT NV·Filed 2014·Granted Dec 16, 2014·1 cites·26 claims
- 0849US9147453B2Programmable delay introducing circuit in self timed memoryST MICROELECTRONICS INT NV·Filed 2014·Granted Sep 29, 2015·0 cites·17 claims
- 0945US8963053B2Programmable delay introducing circuit in self-timed memoryKOHLI NISHU·Filed 2012·Granted Feb 24, 2015·0 cites·14 claims
- 1040US8138455B2Programmable delay introducing circuit in self timed memoryKOHLI NISHU·Filed 2006·Granted Mar 20, 2012·0 cites·6 claims
- 1138US9324414B2Selective dual cycle write operation for a self-timed memoryST MICROELECTRONICS INT NV·Filed 2013·Granted Apr 26, 2016·0 cites·24 claims
- 1235US8854901B2Read self timing circuitry for self-timed memoryKOHLI NISHU·Filed 2012·Granted Oct 7, 2014·0 cites·25 claims
- 1335US8854902B2Write self timing circuitry for self-timed memoryKOHLI NISHU·Filed 2012·Granted Oct 7, 2014·0 cites·30 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →