Inventor · disambiguated record
Niranjan Kulkarni
Also filed as: KULKARNI NIRANJAN
9 granted patents·71 citations·filing 2013–2017
87Inventor score
Top patents by PatentIndex Score
9 records- 0191US9876503B2Method of obfuscating digital logic circuits using threshold voltageVRUDHULA SARMA·Filed 2016·Granted Jan 23, 2018·16 cites·19 claims
- 0288US8832614B2Technology mapping for threshold and logic gate hybrid circuitsVRUDHULA SARMA·Filed 2013·Granted Sep 9, 2014·13 cites·8 claims
- 0387US10447249B2Hold violation free scan chain and scanning mechanism for testing of synchronous digital VLSI circuitsVRUDHULA SARMA·Filed 2016·Granted Oct 15, 2019·4 cites·18 claims
- 0487US9473139B2Threshold logic element with stabilizing feedbackVRUDHULA SARMA·Filed 2015·Granted Oct 18, 2016·7 cites·18 claims
- 0587US9356598B2Threshold logic gates with resistive networksVRUDHULA SARMA·Filed 2015·Granted May 31, 2016·8 cites·20 claims
- 0686US9490815B2Robust, low power, reconfigurable threshold logic arrayUNIV ARIZONA STATE·Filed 2014·Granted Nov 8, 2016·7 cites·29 claims
- 0783US10551869B2Clock skewing strategy to reduce dynamic power and eliminate hold-time violations in synchronous digital VLSI designsVRUDHULA SARMA·Filed 2017·Granted Feb 4, 2020·5 cites·17 claims
- 0882US9306151B2Threshold gate and threshold logic arrayUNIV ARIZONA·Filed 2013·Granted Apr 5, 2016·6 cites·27 claims
- 0981US10250236B2Energy efficient, robust differential mode d-flip-flopVRUDHULA SARMA·Filed 2016·Granted Apr 2, 2019·5 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →