Inventor · disambiguated record
Nicolas Loubet
Also filed as: LOUBET NICOLAS · LOUBET NICOLAS J · LOUBET NICOLAS JEAN
285 granted patents·88 pending applications·1,409 citations·filing 2006–2024
99Inventor score
Files withIBM213ST MICROELECTRONICS INC97COMMISSARIAT ENERGIE ATOMIQUE11GLOBALFOUNDRIES INC11BELL SEMICONDUCTOR LLC8
Top patents by PatentIndex Score
373 records- 0199US10388732B1Nanosheet field-effect transistors including a two-dimensional semiconducting materialGLOBALFOUNDRIES INC·Filed 2018·Granted Aug 20, 2019·88 cites·20 claims
- 0299US10074575B1Integrating and isolating nFET and pFET nanosheet transistors on a substrateIBM·Filed 2017·Granted Sep 11, 2018·45 cites·19 claims
- 0399US9755017B1Co-integration of silicon and silicon-germanium channels for nanosheet devicesIBM·Filed 2016·Granted Sep 5, 2017·48 cites·18 claims
- 0499US9716158B1Air gap spacer between contact and gate regionIBM·Filed 2016·Granted Jul 25, 2017·111 cites·19 claims
- 0598US12154971B2Forming nanosheet transistor using sacrificial spacer and inner spacersADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Nov 26, 2024·2 cites·20 claims
- 0698US10573755B1Nanosheet FET with box isolation on substrateIBM·Filed 2018·Granted Feb 25, 2020·32 cites·19 claims
- 0798US10424651B2Forming nanosheet transistor using sacrificial spacer and inner spacersIBM·Filed 2018·Granted Sep 24, 2019·16 cites·13 claims
- 0898US10367061B1Replacement metal gate and inner spacer formation in three dimensional structures using sacrificial silicon germaniumIBM·Filed 2018·Granted Jul 30, 2019·23 cites·20 claims
- 0998US10276442B1Wrap-around contacts formed with multiple silicide layersGLOBALFOUNDRIES INC·Filed 2018·Granted Apr 30, 2019·29 cites·20 claims
- 1098US9761722B1Isolation of bulk FET devices with embedded stressorsIBM·Filed 2016·Granted Sep 12, 2017·25 cites·18 claims
- 1198US9741626B1Vertical transistor with uniform bottom spacer formed by selective oxidationIBM·Filed 2016·Granted Aug 22, 2017·47 cites·8 claims
- 1298US8956942B2Method of forming a fully substrate-isolated FinFET transistorST MICROELECTRONICS INC·Filed 2012·Granted Feb 17, 2015·41 cites·16 claims
- 1398US8569152B1Cut-very-last dual-epi flowBASKER VEERARAGHAVAN S·Filed 2012·Granted Oct 29, 2013·65 cites·20 claims
- 1497US10109533B1Nanosheet devices with CMOS epitaxy and method of formingGLOBALFOUNDRIES INC·Filed 2017·Granted Oct 23, 2018·23 cites·10 claims
- 1597US10020398B1Stress induction in 3D device channel using elastic relaxation of high stress materialIBM·Filed 2017·Granted Jul 10, 2018·12 cites·18 claims
- 1697US8952420B1Method to induce strain in 3-D microfabricated structuresST MICROELECTRONICS INC·Filed 2013·Granted Feb 10, 2015·19 cites·12 claims
- 1797US8759874B1FinFET device with isolated channelST MICROELECTRONICS INC·Filed 2012·Granted Jun 24, 2014·31 cites·20 claims
- 1896US11894436B2Gate-all-around monolithic stacked field effect transistors having multiple threshold voltagesIBM·Filed 2021·Granted Feb 6, 2024·3 cites·14 claims
- 1996US10903315B2Formation of dielectric layer as etch-stop for source and drain epitaxy disconnectionIBM·Filed 2018·Granted Jan 26, 2021·12 cites·13 claims
- 2096US10566445B2Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between gatesIBM·Filed 2018·Granted Feb 18, 2020·11 cites·10 claims
- 2196US10170520B1Negative-capacitance steep-switch field effect transistor with integrated bi-stable resistive systemIBM·Filed 2018·Granted Jan 1, 2019·19 cites·20 claims
- 2296US8975168B2Method for the formation of fin structures for FinFET devicesST MICROELECTRONICS INC·Filed 2013·Granted Mar 10, 2015·23 cites·22 claims
- 2395US10998234B2Nanosheet bottom isolation and source or drain epitaxial growthIBM·Filed 2019·Granted May 4, 2021·11 cites·20 claims
- 2495US9679780B1Polysilicon residue removal in nanosheet MOSFETsIBM·Filed 2016·Granted Jun 13, 2017·11 cites·20 claims
- 2595US9466718B2Semiconductor device with fin and related methodsST MICROELECTRONICS INC·Filed 2015·Granted Oct 11, 2016·8 cites·17 claims
- 2695US9093496B2Process for faciltiating fin isolation schemesGLOBALFOUNDRIES INC·Filed 2013·Granted Jul 28, 2015·19 cites·21 claims
- 2794US11081547B2Method for making superimposed transistorsCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2019·Granted Aug 3, 2021·8 cites·15 claims
- 2894US10748901B2Interlayer via contacts for monolithic three-dimensional semiconductor integrated circuit devicesIBM·Filed 2018·Granted Aug 18, 2020·11 cites·15 claims
- 2994US10741660B2Nanosheet single gate (SG) and extra gate (EG) field effect transistor (FET) co-integrationIBM·Filed 2018·Granted Aug 11, 2020·9 cites·7 claims
- 3094US10242920B2Integrating and isolating NFET and PFET nanosheet transistors on a substrateIBM·Filed 2018·Granted Mar 26, 2019·7 cites·20 claims
- 3194US8592290B1Cut-very-last dual-EPI flowBASKER VEERARAGHAVAN S·Filed 2012·Granted Nov 26, 2013·16 cites·20 claims
- 3293US11587928B2Method to induce strain in finFET channels from an adjacent regionBELL SEMICONDUCTOR LLC·Filed 2020·Granted Feb 21, 2023·2 cites·14 claims
- 3393US10546942B2Nanosheet transistor with optimized junction and cladding defectivity controlIBM·Filed 2017·Granted Jan 28, 2020·7 cites·13 claims
- 3493US10249739B2Nanosheet MOSFET with partial release and source/drain epitaxyIBM·Filed 2017·Granted Apr 2, 2019·9 cites·18 claims
- 3593US10062690B2Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methodsST MICROELECTRONICS INC·Filed 2016·Granted Aug 28, 2018·5 cites·16 claims
- 3693US9735062B1Defect reduction in channel silicon germanium on patterned siliconIBM·Filed 2016·Granted Aug 15, 2017·9 cites·20 claims
- 3793US9716086B1Method and structure for forming buried ESD with FinFETsIBM·Filed 2016·Granted Jul 25, 2017·7 cites·10 claims
- 3893US9520393B2Fully substrate-isolated FinFET transistorST MICROELECTRONICS INC·Filed 2014·Granted Dec 13, 2016·9 cites·21 claims
- 3993US9245953B2Method to induce strain in 3-D microfabricated structuresST MICROELECTRONICS INC·Filed 2015·Granted Jan 26, 2016·6 cites·32 claims
- 4093US9093556B2Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methodsLIU QING·Filed 2012·Granted Jul 28, 2015·9 cites·12 claims
- 4193US9018057B1Method of making a CMOS semiconductor device using a stressed silicon-on-insulator (SOI) waferST MICROELECTRONICS INC·Filed 2013·Granted Apr 28, 2015·10 cites·27 claims
- 4292US10971490B2Three-dimensional field effect deviceIBM·Filed 2018·Granted Apr 6, 2021·6 cites·20 claims
- 4392US10832964B1Replacement contact formation for gate contact over active region with selective metal growthIBM·Filed 2019·Granted Nov 10, 2020·8 cites·20 claims
- 4492US10515965B2Method to induce strain in finFET channels from an adjacent regionST MICROELECTRONICS INC·Filed 2018·Granted Dec 24, 2019·4 cites·20 claims
- 4592US10483393B2Method to induce strain in 3-D microfabricated structuresST MICROELECTRONICS INC·Filed 2017·Granted Nov 19, 2019·4 cites·21 claims
- 4692US10256316B1Steep-switch field effect transistor with integrated bi-stable resistive systemIBM·Filed 2018·Granted Apr 9, 2019·7 cites·9 claims
- 4792US9978678B1Vertically integrated nanosheet fuseIBM·Filed 2017·Granted May 22, 2018·5 cites·4 claims
- 4892US9685380B2Method to co-integrate SiGe and Si channels for finFET devicesST MICROELECTRONICS INC·Filed 2013·Granted Jun 20, 2017·8 cites·15 claims
- 4992US9679899B2Co-integration of tensile silicon and compressive silicon germaniumST MICROELECTRONICS INC·Filed 2015·Granted Jun 13, 2017·5 cites·20 claims
- 5092US9418900B1Silicon germanium and silicon fins on oxide from bulk waferIBM·Filed 2015·Granted Aug 16, 2016·7 cites·20 claims
Showing the top 50 of 373 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →