Inventor · disambiguated record
Nivo Rovedo
Also filed as: ROVEDO NIVO
42 granted patents·3 pending applications·1,469 citations·filing 1983–2012
98Inventor score
Top patents by PatentIndex Score
45 records- 0197US4648937AMethod of preventing asymmetric etching of lines in sub-micrometer range sidewall images transferIBM·Filed 1985·Granted Mar 10, 1987·348 cites·18 claims
- 0295US4671851AMethod for removing protuberances at the surface of a semiconductor wafer using a chem-mech polishing techniqueIBM·Filed 1985·Granted Jun 9, 1987·189 cites·15 claims
- 0394US7279758B1N-channel MOSFETs comprising dual stressors, and methods for forming the sameIBM·Filed 2006·Granted Oct 9, 2007·24 cites·7 claims
- 0492US4868135AMethod for manufacturing a Bi-CMOS deviceIBM·Filed 1988·Granted Sep 19, 1989·77 cites·21 claims
- 0591US7442618B2Method to engineer etch profiles in Si substrate for advanced semiconductor devicesCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Oct 28, 2008·22 cites·21 claims
- 0690US6403482B1Self-aligned junction isolationIBM·Filed 2000·Granted Jun 11, 2002·58 cites·6 claims
- 0789US7960798B2Structure and method to form multilayer embedded stressorsIBM·Filed 2009·Granted Jun 14, 2011·11 cites·10 claims
- 0888US7618866B2Structure and method to form multilayer embedded stressorsIBM·Filed 2006·Granted Nov 17, 2009·11 cites·9 claims
- 0988US6429091B1Patterned buried insulatorIBM·Filed 2000·Granted Aug 6, 2002·55 cites·8 claims
- 1087US6544874B2Method for forming junction on insulator (JOI) structureIBM·Filed 2001·Granted Apr 8, 2003·48 cites·36 claims
- 1183US7442619B2Method of forming substantially L-shaped silicide contact for a semiconductor deviceIBM·Filed 2006·Granted Oct 28, 2008·9 cites·2 claims
- 1282US5622881APacking density for flash memoriesIBM·Filed 1994·Granted Apr 22, 1997·42 cites·10 claims
- 1381US5369049ADRAM cell having raised source, drain and isolationIBM·Filed 1993·Granted Nov 29, 1994·45 cites·8 claims
- 1480US7785950B2Dual stress memory technique method and related structureIBM·Filed 2005·Granted Aug 31, 2010·9 cites·13 claims
- 1580US5654917AProcess for making and programming a flash memory arrayIBM·Filed 1996·Granted Aug 5, 1997·47 cites·4 claims
- 1677US8482075B2Structure and method for manufacturing asymmetric devicesNAYFEH HASAN M·Filed 2012·Granted Jul 9, 2013·4 cites·6 claims
- 1777US8017483B2Method of creating asymmetric field-effect-transistorsIBM·Filed 2009·Granted Sep 13, 2011·5 cites·26 claims
- 1877US4729006ASidewall spacers for CMOS circuit stress relief/isolation and method for makingIBM·Filed 1986·Granted Mar 1, 1988·51 cites·15 claims
- 1976US5541130AProcess for making and programming a flash memory arrayIBM·Filed 1995·Granted Jul 30, 1996·39 cites·12 claims
- 2075US7473608B2N-channel MOSFETs comprising dual stressors, and methods for forming the sameIBM·Filed 2007·Granted Jan 6, 2009·4 cites·18 claims
- 2175US4641170ASelf-aligned lateral bipolar transistorsIBM·Filed 1985·Granted Feb 3, 1987·32 cites·8 claims
- 2273US6352903B1Junction isolationIBM·Filed 2000·Granted Mar 5, 2002·24 cites·6 claims
- 2371US6525340B2Semiconductor device with junction isolationIBM·Filed 2001·Granted Feb 25, 2003·16 cites·13 claims
- 2471US5650345AMethod of making self-aligned stacked gate EEPROM with improved coupling ratioIBM·Filed 1995·Granted Jul 22, 1997·27 cites·4 claims
- 2570US6916729B2Salicide formation methodIBM·Filed 2003·Granted Jul 12, 2005·16 cites·11 claims
- 2670US5643813APacking density for flash memories by using a pad oxideIBM·Filed 1995·Granted Jul 1, 1997·30 cites·5 claims
- 2769US5892257APacking density for flash memoriesIBM·Filed 1996·Granted Apr 6, 1999·30 cites·15 claims
- 2869US4551906AMethod for making self-aligned lateral bipolar transistorsIBM·Filed 1983·Granted Nov 12, 1985·21 cites·10 claims
- 2967US8034692B2Structure and method for manufacturing asymmetric devicesIBM·Filed 2009·Granted Oct 11, 2011·2 cites·7 claims
- 3067US6391703B1Buried strap for DRAM using junction isolation techniqueIBM·Filed 2001·Granted May 21, 2002·11 cites·7 claims
- 3164US5681770AProcess for making and programming a flash memory arrayIBM·Filed 1996·Granted Oct 28, 1997·22 cites·12 claims
- 3259US5264395AThin SOI layer for fully depleted field effect transistorsIBM·Filed 1992·Granted Nov 23, 1993·33 cites·8 claims
- 3358US6256755B1Apparatus and method for detecting defective NVRAM cellsIBM·Filed 1998·Granted Jul 3, 2001·16 cites·12 claims
- 3455US5672892AProcess for making and programming a flash memory arrayIBM·Filed 1996·Granted Sep 30, 1997·14 cites·2 claims
- 3554US4982257AVertical bipolar transistor with collector and base extensionsIBM·Filed 1989·Granted Jan 1, 1991·16 cites·16 claims
- 3653US4957875AVertical bipolar transistorIBM·Filed 1988·Granted Sep 18, 1990·17 cites·5 claims
- 3752US8643119B2Substantially L-shaped silicide for contactLUO ZHIJIONG·Filed 2008·Granted Feb 4, 2014·0 cites·6 claims
- 3852US6071767AHigh performance/high density BICMOS processIBM·Filed 1992·Granted Jun 6, 2000·21 cites·19 claims
- 3951US5334281AMethod of forming thin silicon mesas having uniform thicknessIBM·Filed 1992·Granted Aug 2, 1994·22 cites·10 claims
- 4047US8232151B2Structure and method for manufacturing asymmetric devicesNAYFEH HASAN M·Filed 2011·Granted Jul 31, 2012·0 cites·11 claims
- 4142US2007293016A1Semiconductor structure including isolation region with variable linewidth and method for fabrication therofIBM·Filed 2006·Application pending·0 cites
- 4242US2009057755A1Spacer undercut filler, method of manufacture thereof and articles comprising the sameIBM·Filed 2007·Application pending·0 cites
- 4341US6624486B2Method for low topography semiconductor device formationIBM·Filed 2001·Granted Sep 23, 2003·1 cites·10 claims
- 4437US2007134861A1Semiconductor devices and methods of manufacture thereofHAN JIN-PING·Filed 2005·Application pending·0 cites
- 4536US6797569B2Method for low topography semiconductor device formationIBM·Filed 2003·Granted Sep 28, 2004·0 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →