Spacer undercut filler, method of manufacture thereof and articles comprising the same

Abstract

Disclosed herein is a semiconducting device comprising a gate stack formed on a surface of a semiconductor substrate; a vertical nitride spacer element formed on each vertical sidewall of the gate stack; a portion of the vertical nitride spacer overlying the semiconductor substrate; a silicide contact formed on the semiconductor substrate adjacent the gate stack, the silicide contact being in operative communication with drain and source regions formed in the semiconductor substrate; and an oxide spacer disposed between the vertical nitride spacer element and the silicide contact; the oxide spacer operating to minimize an undercut adjacent the vertical nitride spacer during an etching process.

1 . A semiconducting device comprising:
 a gate stack formed on a surface of a semiconductor substrate;   a vertical nitride spacer element formed on each vertical sidewall of the gate stack; a portion of the vertical nitride spacer overlying the semiconductor substrate;   a silicide contact formed on the semiconductor substrate adjacent the gate stack, the silicide contact being in operative communication with drain and source regions formed in the semiconductor substrate; and   an oxide spacer disposed between the vertical nitride spacer element and the silicide contact; the oxide spacer operating to minimize an undercut adjacent the vertical nitride spacer during an etching process.   
   
   
       2 . The semiconducting device of  claim 1 , further comprising a gate dielectric layer disposed atop the semiconductor substrate. 
   
   
       3 . The semiconducting device of  claim 1 , wherein the semiconductor substrate comprises silicon, germanium, silicon-germanium, gallium-arsenide (GaAs), indium-arsenide (InAs), indium-phosphorus (InP), Si/Si, Si/SiGe, silicon-on-insulators, or a combination comprising at least one of the foregoing. 
   
   
       4 . The semiconducting device of  claim 1 , wherein the oxide spacer comprises an oxide selected from the group consisting of SiO 2 , ZrO 2 , Ta 2 O 5 , HfO 2 , Al 2 O 3 , and a combination comprising at least one of the foregoing oxides. 
   
   
       5 . An article comprising the semiconducting device of  claim 1 . 
   
   
       6 . A method comprising:
 disposing a gate stack upon a semiconductor substrate;   disposing a vertical nitride spacer element on each vertical sidewall of the gate stack; a portion of the vertical nitride spacer overlying the semiconductor substrate;   disposing a silicide contact on the semiconductor substrate adjacent the gate stack; and   disposing an oxide spacer between the vertical nitride spacer element and the silicide contact; the oxide spacer operating to minimize an undercut adjacent the vertical nitride spacer during an etching process.   
   
   
       7 . The method of  claim 6 , wherein the disposing of the oxide spacer between the vertical nitride spacer element and the silicide contact comprises:
 disposing a layer of oxide upon exposed surfaces of the semiconductor substrate, the gate stack and the vertical nitride spacer elements;   etching the layer of oxide from the exposed surfaces of the semiconductor substrate, the gate stack and the vertical nitride spacer elements and retaining a portion of the layer of oxide that is disposed between the vertical nitride spacer element and the silicide contact.   
   
   
       8 . The method of  claim 6 , further comprising performing a spacer proximity etch. 
   
   
       9 . The method of  claim 6 , wherein the oxide is a low temperature oxide selected from the group consisting of SiO 2 , ZrO 2 , Ta 2 O 5 , HfO 2 , Al 2 O 3 , and a combination comprising at least one of the foregoing oxides. 
   
   
       10 . The method of  claim 6 , wherein the low temperature oxide spacer has a thickness of about 10 Angstroms to about 300 Angstroms. 
   
   
       11 . An article manufactured by the method of  claim 6 .