Inventor · disambiguated record
Nicholas Samra
Also filed as: SAMRA NICHOLAS · SAMRA NICHOLAS G
22 granted patents·9 pending applications·658 citations·filing 1993–2009
96Inventor score
Top patents by PatentIndex Score
31 records- 0190US8860199B2Multi-die processorBLACK BRYAN P·Filed 2009·Granted Oct 14, 2014·35 cites·16 claims
- 0290US5646878AContent addressable memory systemMOTOROLA INC·Filed 1995·Granted Jul 8, 1997·90 cites·7 claims
- 0388US5809530AMethod and apparatus for processing multiple cache misses using reload folding and store mergingMOTOROLA INC·Filed 1995·Granted Sep 15, 1998·164 cites·16 claims
- 0485US6560671B1Method and apparatus for accelerating exchange or swap instructions using a register alias table (RAT) and content addressable memory (CAM) with logical register numbers as input addressesINTEL CORP·Filed 2000·Granted May 6, 2003·46 cites·24 claims
- 0582US5448722AMethod and system for data processing system error diagnosis utilizing hierarchical blackboard diagnostic sessionsIBM·Filed 1993·Granted Sep 5, 1995·103 cites·12 claims
- 0681US7051190B2Intra-instruction fusionINTEL CORP·Filed 2002·Granted May 23, 2006·36 cites·13 claims
- 0774US6470435B2Dual state rename recovery using register usageINTEL CORP·Filed 2000·Granted Oct 22, 2002·20 cites·21 claims
- 0871US7398372B2Fusing load and alu operationsINTEL CORP·Filed 2002·Granted Jul 8, 2008·15 cites·34 claims
- 0969US6907518B1Pipelined, superscalar floating point unit having out-of-order execution capability and processor employing the sameNAT SEMICONDUCTOR CORP·Filed 2003·Granted Jun 14, 2005·13 cites·20 claims
- 1067US6519683B2System and method for instruction cache re-orderingINTEL CORP·Filed 2000·Granted Feb 11, 2003·12 cites·25 claims
- 1166US6889314B2Method and apparatus for fast dependency coordinate matchingINTEL CORP·Filed 2001·Granted May 3, 2005·12 cites·29 claims
- 1262US7669203B2Virtual multithreading translation mechanism including retrofit capabilityINTEL CORP·Filed 2003·Granted Feb 23, 2010·9 cites·21 claims
- 1361US7246219B2Methods and apparatus to control functional blocks within a processorINTEL CORP·Filed 2003·Granted Jul 17, 2007·8 cites·26 claims
- 1461US7080236B2Updating stack pointer based on instruction bit indicator without executing an update microinstructionINTEL CORP·Filed 2002·Granted Jul 18, 2006·7 cites·33 claims
- 1560US5765208AMethod of speculatively executing store instructions prior to performing snoop operationsMOTOROLA INC·Filed 1995·Granted Jun 9, 1998·43 cites·5 claims
- 1653US7653904B2System for forming a critical update loop to continuously reload active thread state from a register storing thread state until another active thread is detectedINTEL CORP·Filed 2003·Granted Jan 26, 2010·3 cites·9 claims
- 1752US7308563B2Dual-target block register allocationINTEL CORP·Filed 2001·Granted Dec 11, 2007·2 cites·35 claims
- 1850US8694976B2Sleep state mechanism for virtual multithreadingSAMRA NICHOLAS G·Filed 2003·Granted Apr 8, 2014·3 cites·30 claims
- 1946US8219836B2Methods and apparatus to monitor instruction types and control power consumption within a processorSAMRA NICHOLAS G·Filed 2007·Granted Jul 10, 2012·0 cites·15 claims
- 2045US2005127490A1Multi-die processorFiled 2003·Application pending·0 cites
- 2145US2006123219A1Intra-instruction fusionSAMRA NICHOLAS G·Filed 2006·Application pending·0 cites
- 2244US2005138333A1Thread switching mechanismFiled 2003·Application pending·0 cites
- 2344US2005071518A1Flag value renamingINTEL CORP·Filed 2003·Application pending·0 cites
- 2443US6581155B1Pipelined, superscalar floating point unit having out-of-order execution capability and processor employing the sameNAT SEMICONDUCTOR CORP·Filed 1999·Granted Jun 17, 2003·14 cites·20 claims
- 2543US6412063B1Multiple-operand instruction in a two operand pipeline and processor employing the sameVIA CYRIX INC·Filed 1999·Granted Jun 25, 2002·15 cites·20 claims
- 2641US2005228971A1Buffer virtualizationSAMRA NICHOLAS G·Filed 2004·Application pending·0 cites
- 2741US2005251662A1Secondary register file mechanism for virtual multithreadingSAMRA NICHOLAS G·Filed 2004·Application pending·0 cites
- 2841US2002087831A1Instruction packetization based on rename capacityFiled 2000·Application pending·0 cites
- 2941US2002124158A1Virtual r0 registerFiled 2000·Application pending·0 cites
- 3040US2004268093A1Cross-thread register sharing techniqueSAMRA NICHOLAS G·Filed 2003·Application pending·0 cites
- 3136US6275926B1System and method for writing back multiple results over a single-result bus and processor employing the sameVIA CYRIX INC·Filed 1999·Granted Aug 14, 2001·8 cites·28 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →