Intra-instruction fusion

Abstract

Fusing micro-operations (uops) together. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops are fused, stored in a cache memory, un-fused, executed in parallel, and retired in order to optimize cost and performance.

1 . An apparatus comprising: 
 a receiving unit to receive a fused micro-operation (uop), said fused uop comprising data corresponding to at least two uops from a same instruction;    an unfusing unit to unfuse said fused uop into a plurality of child uops, said plurality of child uops comprising a store-address child uop, a store-data child uop, and a stack-pointer update child uop.    
     
     
         2 . The apparatus of  claim 1  further comprising a plurality of execution units to execute said plurality child uops in parallel.  
     
     
         3 . The apparatus of  claim 2  further comprising a rename unit to: 
 assign a first source field of said fused uop to a first source register of said load child uop;    assign a second source field of said fused uop to a second source register of said load child uop;    assign an additional destination field of said fused uop to a destination register of said load child uop;    assign said additional destination field of said fused uop to a first source register of said arithmetic child uop.    assign a first destination field of said fused uop to a second source register and a destination register of said arithmetic child uop.    
     
     
         4 . The apparatus of  claim 3  wherein said unfusing unit and said rename unit are the same functional unit.  
     
     
         5 . The apparatus of  claim 3  wherein said unfusing unit and said rename unit are separate functional units.  
     
     
         6 . The apparatus of  claim 3  wherein each of said plurality of execution units are able to execute an opcode corresponding to only one of said plurality of child uops.  
     
     
         7 . The apparatus of  claim 6  further comprising a retirement unit to retire said instruction after said plurality of child uops have been executed by said plurality of execution units.  
     
     
         8 . The apparatus of  claim 7  wherein only one of said plurality of child uops may generate an exception.  
     
     
         9 . The apparatus of  claim 8  further comprising a plurality of scheduling units to schedule said plurality of child uops in parallel for execution by said plurality of execution units.  
     
     
         10 . An apparatus comprising: 
 a receiving unit to receive a fused micro-operation (uop), said fused uop comprising data corresponding to at least two uops from a same instruction;    an unfusing unit to unfuse said fused uop into a plurality of child uops, plurality of child uops comprising a store-address child uop and a store-data child uop.    
     
     
         11 . The apparatus of  claim 10  further comprising a plurality of execution units to execute said plurality child uops in parallel.  
     
     
         12 . The apparatus of  claim 11  further comprising a rename unit to: 
 assign a first source field of said fused uop to a first source register of said store-address child uop;    assign a second source field of said fused uop to a second source register of said store-address child uop;    assign a destination field of said fused uop to a second source register of said store-data child uop;    assign a null value to a destination register of said store-address child uop, a first source of said store-data child uop, and a destination register of said store-data child uop.    
     
     
         13 . The apparatus of  claim 12  wherein said rename unit and said unfusing unit are one functional unit.  
     
     
         14 . The apparatus of  claim 12  wherein said rename unit and said unfusing unit are separate functional units.  
     
     
         15 . The apparatus of  claim 12  wherein each of said plurality of execution units are able to execute an opcode corresponding to only one of said plurality of child uops.  
     
     
         16 . The apparatus of  claim 15  further comprising a retirement unit to retire said instruction after said plurality of child uops have been executed by said plurality of execution units.  
     
     
         17 . The apparatus of  claim 15  wherein only one of said plurality of child uops may generate an exception.  
     
     
         18 . The apparatus of  claim 16  further comprising a plurality of scheduling units to schedule said plurality of child uops in parallel for execution by said plurality of execution units.  
     
     
         19 . An apparatus comprising: 
 a receiving unit to receive a fused micro-operation (uop), said fused uop comprising data corresponding to a plurality of uops from a same instruction;    an unfusing unit to unfuse said fused uop into a plurality of child uops, said plurality of child uops comprising a condition update flag child uop and an arithmetic child uop.    
     
     
         20 . The apparatus of  claim 19  further comprising a plurality of execution units to execute said plurality child uops in parallel.  
     
     
         21 . The apparatus of  claim 20  further comprising a rename unit to: 
 assign a first source field of said fused uop to a first source register of said condition flag update child uop;    assign a second source field of said fused uop to a second source register of said condition flag update child uop;    assign a destination field of said fused uop to a second source register and a destination register of said arithmetic child uop;    assign a null value to a first source register of said arithmetic child uop.    
     
     
         22 . The apparatus of  claim 21  wherein said rename unit and said unfusing unit are one functional unit.  
     
     
         23 . The apparatus of  claim 21  wherein said rename unit and said unfusing unit are separate functional units.  
     
     
         24 . The apparatus of  claim 21  wherein each of said plurality of execution units are able to execute an opcode corresponding to only one of said plurality of child uops.  
     
     
         25 . The apparatus of  claim 24  further comprising a retirement unit to retire said instruction after said plurality of child uops have been executed by said plurality of execution units.  
     
     
         26 . The apparatus of  claim 25  wherein only one of said plurality of child uops may generate an exception.  
     
     
         27 . The apparatus of  claim 26  further comprising a plurality of scheduling units to schedule said plurality of child uops in parallel for execution by said plurality of execution units.  
     
     
         28 . The apparatus of  claim 19  wherein said arithmetic child uop is an add+1 child uop.  
     
     
         29 . The apparatus of  claim 19  wherein said arithmetic child uop is a sub−1 child uop.  
     
     
         30 . A system comprising: 
 a fusing unit to fuse a plurality of micro-operations (uops) of the same instruction into a fused uop;    a cache entry in which to store said fused uop;    a microprocessor comprising an unfusing unit to unfuse said fused uop into a plurality of child uops.    
     
     
         31 . The system of  claim 30  wherein said microprocessor further comprises a plurality of execution units to execute said plurality of child uops in parallel.  
     
     
         32 . The system of  claim 31  further comprising a rename unit to assign a plurality of uop fields associated with said fused uop to a plurality of registers associated with said plurality of child uops.  
     
     
         33 . The system of  claim 32  wherein said plurality of execution units are able to execute an opcode corresponding to only one of said plurality of child uops.  
     
     
         34 . The system of  claim 33  wherein said microprocessor further comprises a retirement unit to retire said instruction after said plurality of child uops have been executed by said plurality of execution units.  
     
     
         35 . The system of  claim 34  wherein said cache entry is within said microprocessor.  
     
     
         36 . The system of  claim 34  wherein said cache entry is outside of said microprocessor.  
     
     
         37 . The system of  claim 30  wherein said instruction is either a pop instruction, a return instruction, a store instruction, an increment instruction, a decrement instruction, a push instruction, or a call instruction.  
     
     
         38 . A machine-readable medium having stored thereon a set of instructions, which when executed by a machine, cause said machine to perform a method comprising: 
 fusing a plurality of micro-operations (uops) associated with an instruction into a fused uop;    storing said fused uop within a single cache entry;    introducing said fused uop to a microprocessor pipeline;    unfusing said fused uop into a plurality of child uops;    scheduling said plurality of child uops for execution;    executing said plurality of child uops;    retiring said instruction after said plurality of child uops have been executed.    
     
     
         39 . The machine-readable medium of  claim 38  wherein said instruction is a store instruction.  
     
     
         40 . The machine-readable medium of  claim 38  wherein said instruction is an increment or a decrement instruction.  
     
     
         41 . The machine-readable medium of  claim 38  wherein said instruction is a pop or return instruction.  
     
     
         42 . The machine-readable medium of  claim 38  wherein said instruction is a push or call instruction.  
     
     
         43 . The machine-readable medium of  claim 38  wherein said unfusing comprises assigning a fused uop logical register field to a physical register associated with at least one of said plurality of child uops.  
     
     
         44 . The machine-readable medium of  claim 43  wherein said plurality of child uops are scheduled in parallel.  
     
     
         45 . The machine-readable medium of  claim 44  wherein said plurality of child uops are executed in parallel.