Inventor · disambiguated record
Stephan Jourdan
Also filed as: JOURDAN STEPHAN · JOURDAN STEPHAN J · JOURDAN STEPHAN JEAN
99 granted patents·24 pending applications·1,320 citations·filing 1999–2025
99Inventor score
Top patents by PatentIndex Score
123 records- 0196US7949887B2Independent power control of processing coresINTEL CORP·Filed 2006·Granted May 24, 2011·43 cites·29 claims
- 0292US6912648B2Stick and spoke replay with selectable delaysINTEL CORP·Filed 2001·Granted Jun 28, 2005·78 cites·14 claims
- 0391US8069358B2Independent power control of processing coresGUNTHER STEPHEN H·Filed 2009·Granted Nov 29, 2011·14 cites·6 claims
- 0491US7143273B2Method and apparatus for dynamic branch prediction utilizing multiple stew algorithms for indexing a global historyINTEL CORP·Filed 2003·Granted Nov 28, 2006·76 cites·19 claims
- 0590US6898699B2Return address stack including speculative return address buffer with back pointersINTEL CORP·Filed 2001·Granted May 24, 2005·73 cites·23 claims
- 0689US6549987B1Cache structure for storing variable length dataINTEL CORP·Filed 2000·Granted Apr 15, 2003·49 cites·18 claims
- 0788US12007896B2Apparatuses, systems, and methods for configuring combined private and shared cache levels in a processor-based systemAMPERE COMPUTING LLC·Filed 2022·Granted Jun 11, 2024·3 cites·17 claims
- 0888US8275560B2Power measurement techniques of a system-on-chip (SOC)RADHAKRISHNAN SIVAKUMAR·Filed 2009·Granted Sep 25, 2012·17 cites·24 claims
- 0988US7757065B1Instruction segment recording schemeINTEL CORP·Filed 2000·Granted Jul 13, 2010·55 cites·19 claims
- 1088US7181598B2Prediction of load-store dependencies in a processing agentINTEL CORP·Filed 2002·Granted Feb 20, 2007·52 cites·18 claims
- 1187US6950924B2Passing decoded instructions to both trace cache building engine and allocation module operating in trace cache or decoder reading stateINTEL CORP·Filed 2002·Granted Sep 27, 2005·43 cites·22 claims
- 1286US8782456B2Dynamic and idle power reduction sequence using recombinant clock and power gatingTAN SIN S·Filed 2010·Granted Jul 15, 2014·10 cites·30 claims
- 1386US8103831B2Efficient method and apparatus for employing a micro-op cache in a processorRAPPOPORT LIHU·Filed 2008·Granted Jan 24, 2012·20 cites·20 claims
- 1484US7533252B2Overriding a static prediction with a level-two predictorINTEL CORP·Filed 2006·Granted May 12, 2009·17 cites·12 claims
- 1584US7136992B2Method and apparatus for a stew-based loop predictorINTEL CORP·Filed 2003·Granted Nov 14, 2006·38 cites·36 claims
- 1682US7502912B2Method and apparatus for rescheduling operations in a processorINTEL CORP·Filed 2003·Granted Mar 10, 2009·33 cites·24 claims
- 1782US6675282B2System and method for employing a global bit for page sharing in a linear-addressed cacheINTEL CORP·Filed 2003·Granted Jan 6, 2004·29 cites·36 claims
- 1882US6505293B1Register renaming to optimize identical register valuesINTEL CORP·Filed 1999·Granted Jan 7, 2003·98 cites·11 claims
- 1982US6438673B1Correlated address predictionINTEL CORP·Filed 1999·Granted Aug 20, 2002·99 cites·18 claims
- 2081US11947454B2Apparatuses, systems, and methods for controlling cache allocations in a configurable combined private and shared cache in a processor-based systemAMPERE COMPUTING LLC·Filed 2022·Granted Apr 2, 2024·1 cites·20 claims
- 2181US11880306B2Apparatus, system, and method for configuring a configurable combined private and shared cacheAMPERE COMPUTING LLC·Filed 2022·Granted Jan 23, 2024·1 cites·14 claims
- 2281US6675280B2Method and apparatus for identifying candidate virtual addresses in a content-aware prefetcherINTEL CORP·Filed 2001·Granted Jan 6, 2004·35 cites·41 claims
- 2381US6631445B2Cache structure for storing variable length dataINTEL CORP·Filed 2003·Granted Oct 7, 2003·26 cites·19 claims
- 2480US6952764B2Stopping replay tornadoesINTEL CORP·Filed 2001·Granted Oct 4, 2005·29 cites·17 claims
- 2578US7093077B2Method and apparatus for next-line prefetching from a predicted memory addressINTEL CORP·Filed 2002·Granted Aug 15, 2006·28 cites·33 claims
- 2678US2025231236A1Component die validation built-in self-test (vbist) engineAMPERE COMPUTING LLC·Filed 2025·Application pending·0 cites
- 2777US11526205B2Methods and apparatus to implement always-on context sensor hubs for processing multiple different types of data inputsINTEL CORP·Filed 2018·Granted Dec 13, 2022·2 cites·24 claims
- 2877US9021279B2Independent power control of processing coresGUNTHER STEPHEN H·Filed 2011·Granted Apr 28, 2015·2 cites·18 claims
- 2977US2025224797A1Methods and apparatus to implement always-on context sensor hubs for processing multiple different types of data inputsINTEL CORP·Filed 2025·Application pending·0 cites
- 3076US8850250B2Integration of processor and input/output hubLOOI LILY PAO·Filed 2010·Granted Sep 30, 2014·6 cites·20 claims
- 3175US7404065B2Flow optimization and prediction for VSSE memory operationsINTEL CORP·Filed 2005·Granted Jul 22, 2008·7 cites·23 claims
- 3273US12360585B2Methods and apparatus to implement always-on context sensor hubs for processing multiple different types of data inputsINTEL CORP·Filed 2022·Granted Jul 15, 2025·0 cites·31 claims
- 3373US7017026B2Generating lookahead tracked register value based on arithmetic operation indicationINTEL CORP·Filed 2004·Granted Mar 21, 2006·15 cites·20 claims
- 3473US6594754B1Mapping destination logical register to physical register storing immediate or renamed source register of move instruction and using mapping countersINTEL CORP·Filed 1999·Granted Jul 15, 2003·63 cites·24 claims
- 3572US8397090B2Operating integrated circuit logic blocks at independent voltages with single voltage supplyGUNTHER STEPHEN H·Filed 2006·Granted Mar 12, 2013·6 cites·11 claims
- 3672US8239659B2Vector completion mask handlingJOURDAN STEPHAN·Filed 2006·Granted Aug 7, 2012·6 cites·22 claims
- 3772US7260704B2Method and apparatus for reinforcing a prefetch chainINTEL CORP·Filed 2002·Granted Aug 21, 2007·19 cites·52 claims
- 3872US7243219B2Predicting instruction branches with a plurality of global predictors using varying amounts of history instructionINTEL CORP·Filed 2003·Granted Jul 10, 2007·18 cites·25 claims
- 3971US12282064B2Component die validation built-in self-test (VBIST) engineAMPERE COMPUTING LLC·Filed 2022·Granted Apr 22, 2025·0 cites·35 claims
- 4071US7398372B2Fusing load and alu operationsINTEL CORP·Filed 2002·Granted Jul 8, 2008·15 cites·34 claims
- 4171US7181597B2Decoding instructions for trace cache resume state in system passing decoded operations to both trace cache and execution allocation moduleINTEL CORP·Filed 2005·Granted Feb 20, 2007·4 cites·18 claims
- 4269US7711898B2Register alias table cache to map a logical register to a physical registerINTEL CORP·Filed 2003·Granted May 4, 2010·14 cites·20 claims
- 4367US10635155B2Independent power control of processing coresINTEL CORP·Filed 2018·Granted Apr 28, 2020·0 cites·20 claims
- 4467US10613610B2Independent power control of processing coresINTEL CORP·Filed 2018·Granted Apr 7, 2020·0 cites·20 claims
- 4567US10534419B2Independent power control of processing coresINTEL CORP·Filed 2018·Granted Jan 14, 2020·0 cites·20 claims
- 4667US10095300B2Independent power control of processing coresINTEL CORP·Filed 2017·Granted Oct 9, 2018·0 cites·20 claims
- 4766US7155599B2Method and apparatus for a register renaming structureINTEL CORP·Filed 2000·Granted Dec 26, 2006·11 cites·15 claims
- 4866US6564298B2Front end system having multiple decoding modesINTEL CORP·Filed 2000·Granted May 13, 2003·9 cites·27 claims
- 4965US8572358B2Meta predictor restoration upon detecting mispredictionRONEN RONNY·Filed 2012·Granted Oct 29, 2013·1 cites·20 claims
- 5064US8949635B2Integrated circuit performance improvement across a range of operating conditions and physical constraintsGUNTHER STEPHEN H·Filed 2007·Granted Feb 3, 2015·3 cites·13 claims
Showing the top 50 of 123 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →