Inventor · disambiguated record
Norman Robert Card
Also filed as: CARD NORMAN · CARD NORMAN ROBERT
19 granted patents·58 citations·filing 2011–2024
92Inventor score
Top patents by PatentIndex Score
19 records- 0190US9640280B1Power domain aware insertion methods and designs for testing and repairing memoryCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted May 2, 2017·8 cites·20 claims
- 0287US12007440B1Systems and methods for scan chain stitchingCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Jun 11, 2024·1 cites·20 claims
- 0387US9865362B1Method and apparatus for testing error correction code (ECC) logic and physical memory onboard a manufactured integrated circuit (IC)CADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jan 9, 2018·9 cites·20 claims
- 0484US10095822B1Memory built-in self-test logic in an integrated circuit designCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Oct 9, 2018·4 cites·20 claims
- 0583US8677196B1Low cost production testing for memoryGREGOR STEVEN LEE·Filed 2011·Granted Mar 18, 2014·14 cites·32 claims
- 0679US8719761B2Method and apparatus for optimizing memory-built-in-self testCARD NORMAN·Filed 2012·Granted May 6, 2014·8 cites·44 claims
- 0778US10783299B1Simulation event reduction and power control during MBIST through clock tree managementCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Sep 22, 2020·2 cites·20 claims
- 0877US10387599B1Systems, methods, and computer-readable media utilizing improved data structures and design flow for programmable memory built-in self-test (PMBIST)CADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Aug 20, 2019·2 cites·22 claims
- 0973US8990749B2Method and apparatus for optimizing memory-built-in-self testARORA PUNEET·Filed 2012·Granted Mar 24, 2015·4 cites·20 claims
- 1072US10699795B1System, method and computer-accessible medium for automated identification of embedded physical memories using shared test bus access in intellectual property coresCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Jun 30, 2020·1 cites·21 claims
- 1169US10007489B1Automated method identifying physical memories within a core or macro integrated circuit designCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jun 26, 2018·1 cites·15 claims
- 1267US10319459B1Customizable built-in self-test testplans for memory unitsCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Jun 11, 2019·2 cites·20 claims
- 1358US10593419B1Failing read count diagnostics for memory built-in self-testCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Mar 17, 2020·1 cites·15 claims
- 1454US10541043B1On demand data stream controller for programming and executing operations in an integrated circuitCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Jan 21, 2020·1 cites·19 claims
- 1553US10395747B1Register-transfer level design engineering change order strategyCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Aug 27, 2019·0 cites·22 claims
- 1648US12393246B1Power consumption estimation of memory under testCADENCE DESIGN SYSTEMS INC·Filed 2024·Granted Aug 19, 2025·0 cites·20 claims
- 1741US10504607B1Multiple-channel, programmable fuse control unitCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Dec 10, 2019·0 cites·23 claims
- 1841US10482989B1Dynamic diagnostics analysis for memory built-in self-testCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Nov 19, 2019·0 cites·20 claims
- 1936US10387598B1Verifying results in simulation through simulation add-on to support visualization of selected memory contents in real timeCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Aug 20, 2019·0 cites·7 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →