Inventor · disambiguated record
Omer H. Dokumaci
Also filed as: DOKUMACI OMER · DOKUMACI OMER H
97 granted patents·14 pending applications·2,608 citations·filing 1999–2014
99Inventor score
Top patents by PatentIndex Score
111 records- 0198US7682887B2Transistor having high mobility channel and methodsIBM·Filed 2006·Granted Mar 23, 2010·152 cites·13 claims
- 0298US6977194B2Structure and method to improve channel mobility by gate electrode stress modificationIBM·Filed 2003·Granted Dec 20, 2005·225 cites·5 claims
- 0398US6825529B2Stress inducing spacersIBM·Filed 2002·Granted Nov 30, 2004·234 cites·1 claims
- 0497US7247534B2Silicon device on Si:C-OI and SGOI and method of manufactureIBM·Filed 2003·Granted Jul 24, 2007·95 cites·17 claims
- 0597US7198995B2Strained finFETs and method of manufactureIBM·Filed 2003·Granted Apr 3, 2007·154 cites·26 claims
- 0697US7041538B2Method of manufacturing a disposable reversed spacer process for high performance recessed channel CMOSIBM·Filed 2003·Granted May 9, 2006·124 cites·11 claims
- 0797US6974981B2Isolation structures for imposing stress patternsIBM·Filed 2002·Granted Dec 13, 2005·137 cites·2 claims
- 0896US7060539B2Method of manufacture of FinFET devices with T-shaped fins and devices manufactured therebyIBM·Filed 2004·Granted Jun 13, 2006·123 cites·20 claims
- 0993US7303949B2High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufactureIBM·Filed 2003·Granted Dec 4, 2007·44 cites·3 claims
- 1093US6780694B2MOS transistorIBM·Filed 2003·Granted Aug 24, 2004·67 cites·20 claims
- 1192US7453123B2Self-aligned planar double-gate transistor structureIBM·Filed 2007·Granted Nov 18, 2008·15 cites·1 claims
- 1292US6890808B2Method and structure for improved MOSFETs using poly/silicide gate height controlIBM·Filed 2003·Granted May 10, 2005·60 cites·14 claims
- 1392US6887751B2MOSFET performance improvement using deformation in SOI structureIBM·Filed 2003·Granted May 3, 2005·61 cites·12 claims
- 1491US7176116B2High performance FET with laterally thin extensionIBM·Filed 2005·Granted Feb 13, 2007·17 cites·20 claims
- 1591US7091563B2Method and structure for improved MOSFETs using poly/silicide gate height controlIBM·Filed 2005·Granted Aug 15, 2006·16 cites·7 claims
- 1690US7144787B2Methods to improve the SiGe heterojunction bipolar device performanceIBM·Filed 2005·Granted Dec 5, 2006·16 cites·17 claims
- 1790US7056773B2Backgated FinFET having different oxide thicknessesIBM·Filed 2004·Granted Jun 6, 2006·37 cites·22 claims
- 1890US6869866B1Silicide proximity structures for CMOS device performance improvementsIBM·Filed 2003·Granted Mar 22, 2005·53 cites·23 claims
- 1990US6657244B1Structure and method to reduce silicon substrate consumption and improve gate sheet resistance during silicide formationIBM·Filed 2002·Granted Dec 2, 2003·55 cites·8 claims
- 2089US6677646B2Method and structure of a disposable reversed spacer process for high performance recessed channel CMOSIBM·Filed 2002·Granted Jan 13, 2004·41 cites·9 claims
- 2188US7952149B2Anti-halo compensationIBM·Filed 2005·Granted May 31, 2011·11 cites·2 claims
- 2288US6562713B1Method of protecting semiconductor areas while exposing a gateIBM·Filed 2002·Granted May 13, 2003·42 cites·10 claims
- 2387US7037770B2Method of manufacturing strained dislocation-free channels for CMOSIBM·Filed 2003·Granted May 2, 2006·33 cites·23 claims
- 2486US7595247B2Halo-first ultra-thin SOI FET for superior short channel controlIBM·Filed 2007·Granted Sep 29, 2009·11 cites·11 claims
- 2586US7224021B2MOSFET with high angle sidewall gate and contacts for reduced miller capacitanceIBM·Filed 2005·Granted May 29, 2007·9 cites·12 claims
- 2686US7205185B2Self-aligned planar double-gate process by self-aligned oxidationIBM·Filed 2003·Granted Apr 17, 2007·26 cites·18 claims
- 2786US6914303B2Ultra thin channel MOSFETIBM·Filed 2003·Granted Jul 5, 2005·33 cites·4 claims
- 2886US6806534B2Damascene method for improved MOS transistorIBM·Filed 2003·Granted Oct 19, 2004·35 cites·18 claims
- 2986US6709926B2High performance logic and high density embedded dram with borderless contact and antispacerIBM·Filed 2002·Granted Mar 23, 2004·26 cites·12 claims
- 3086US6686637B1Gate structure with independently tailored vertical doping profileIBM·Filed 2002·Granted Feb 3, 2004·29 cites·14 claims
- 3185US7374987B2Stress inducing spacersIBM·Filed 2004·Granted May 20, 2008·32 cites·7 claims
- 3285US7312134B2Dual stressed SOI substratesIBM·Filed 2007·Granted Dec 25, 2007·10 cites·10 claims
- 3385US6812105B1Ultra-thin channel device with raised source and drain and solid source extension dopingIBM·Filed 2003·Granted Nov 2, 2004·28 cites·15 claims
- 3485US6566210B2Method of improving gate activation by employing atomic oxygen enhanced oxidationIBM·Filed 2001·Granted May 20, 2003·35 cites·20 claims
- 3583US7476914B2Methods to improve the SiGe heterojunction bipolar device performanceIBM·Filed 2006·Granted Jan 13, 2009·8 cites·7 claims
- 3682US7964865B2Strained silicon on relaxed sige film with uniform misfit dislocation densityIBM·Filed 2005·Granted Jun 21, 2011·6 cites·6 claims
- 3782US7144767B2NFETs using gate induced stress modulationIBM·Filed 2003·Granted Dec 5, 2006·24 cites·35 claims
- 3882US6911384B2Gate structure with independently tailored vertical doping profileIBM·Filed 2003·Granted Jun 28, 2005·22 cites·14 claims
- 3982US6645867B2Structure and method to preserve STI during etchingIBM·Filed 2001·Granted Nov 11, 2003·21 cites·18 claims
- 4081US7495291B2Strained dislocation-free channels for CMOS and method of manufactureIBM·Filed 2005·Granted Feb 24, 2009·6 cites·4 claims
- 4181US7026247B2Nanocircuit and self-correcting etching method for fabricating sameIBM·Filed 2003·Granted Apr 11, 2006·21 cites·16 claims
- 4281US6989322B2Method of forming ultra-thin silicidation-stop extensions in mosfet devicesIBM·Filed 2003·Granted Jan 24, 2006·27 cites·17 claims
- 4381US6509221B1Method for forming high performance CMOS devices with elevated sidewall spacersIBM·Filed 2001·Granted Jan 21, 2003·25 cites·12 claims
- 4480US7223994B2Strained Si on multiple materials for bulk or SOI substratesIBM·Filed 2004·Granted May 29, 2007·21 cites·10 claims
- 4579US7262087B2Dual stressed SOI substratesIBM·Filed 2004·Granted Aug 28, 2007·20 cites·15 claims
- 4679US6833569B2Self-aligned planar double-gate process by amorphizationIBM·Filed 2002·Granted Dec 21, 2004·24 cites·17 claims
- 4778US6872641B1Strained silicon on relaxed sige film with uniform misfit dislocation densityIBM·Filed 2003·Granted Mar 29, 2005·16 cites·16 claims
- 4877US8232153B2Silicon device on Si:C-OI and SGOI and method of manufactureCHIDAMBARRAO DURESETI·Filed 2007·Granted Jul 31, 2012·4 cites·20 claims
- 4977US7476946B2Backgated FinFET having different oxide thicknessesIBM·Filed 2006·Granted Jan 13, 2009·5 cites·12 claims
- 5077US7361973B2Embedded stressed nitride liners for CMOS performance improvementIBM·Filed 2004·Granted Apr 22, 2008·17 cites·10 claims
Showing the top 50 of 111 patent records by PatentIndex Score.
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