Assignee
CHIDAMBARRAO DURESETI
US·16 granted patents·1 pending application·80 citations·filing 2005–2012
Top patents by PatentIndex Score
17 records- 0197US8476706B1CMOS having a SiC/SiGe alloy stackCHIDAMBARRAO DURESETI·Filed 2012·Granted Jul 2, 2013·29 cites·12 claims
- 0295US8629022B2Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating sameCHIDAMBARRAO DURESETI·Filed 2012·Granted Jan 14, 2014·18 cites·19 claims
- 0385US8445974B2Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating sameCHIDAMBARRAO DURESETI·Filed 2010·Granted May 21, 2013·7 cites·19 claims
- 0481US8541814B2Minimizing leakage current and junction capacitance in CMOS transistors by utilizing dielectric spacersCHIDAMBARRAO DURESETI·Filed 2011·Granted Sep 24, 2013·4 cites·8 claims
- 0579US8453100B2Circuit analysis using transverse bucketsCHIDAMBARRAO DURESETI·Filed 2010·Granted May 28, 2013·5 cites·20 claims
- 0677US8232153B2Silicon device on Si:C-OI and SGOI and method of manufactureCHIDAMBARRAO DURESETI·Filed 2007·Granted Jul 31, 2012·4 cites·20 claims
- 0769US8232165B2Film wrapped NFET nanowireCHIDAMBARRAO DURESETI·Filed 2011·Granted Jul 31, 2012·4 cites·10 claims
- 0869US8168971B2Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drainCHIDAMBARRAO DURESETI·Filed 2008·Granted May 1, 2012·3 cites·20 claims
- 0966US8296691B2Methodology for improving device performance prediction from effects of active area corner roundingCHIDAMBARRAO DURESETI·Filed 2008·Granted Oct 23, 2012·4 cites·24 claims
- 1060US8405165B2Field effect transistor having multiple conduction statesCHIDAMBARRAO DURESETI·Filed 2005·Granted Mar 26, 2013·2 cites·13 claims
- 1153US8492802B2Multiple orientation nanowires with gate stack sensorsCHIDAMBARRAO DURESETI·Filed 2012·Granted Jul 23, 2013·0 cites·4 claims
- 1253US8299622B2IC having viabar interconnection and related methodCHIDAMBARRAO DURESETI·Filed 2008·Granted Oct 30, 2012·0 cites·17 claims
- 1352US8119472B2Silicon device on Si:C SOI and SiGe and method of manufactureCHIDAMBARRAO DURESETI·Filed 2007·Granted Feb 21, 2012·0 cites·13 claims
- 1450US8492268B2IC having viabar interconnection and related methodCHIDAMBARRAO DURESETI·Filed 2012·Granted Jul 23, 2013·0 cites·6 claims
- 1547US8302040B2Compact model methodology for PC landing pad lithographic rounding impact on device performanceCHIDAMBARRAO DURESETI·Filed 2011·Granted Oct 30, 2012·0 cites·5 claims
- 1646US2005280051A1Isolation structures for imposing stress patternsCHIDAMBARRAO DURESETI·Filed 2005·Application pending·0 cites
- 1733US8237150B2Nanowire devices for enhancing mobility through stress engineeringCHIDAMBARRAO DURESETI·Filed 2009·Granted Aug 7, 2012·0 cites·23 claims
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