Multiple orientation nanowires with gate stack sensors

Abstract

An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness t C ; and a dielectric film of thickness t g in contact with a surface of the channel. Further, the film comprises a material that exerts one of a compressive or a tensile force on the contacted surface of the channel such that electrical mobility of the charge carriers (electrons or holes) along the channel length is increased due to the compressive or tensile force in dependence on alignment of the channel length relative to the crystal structure. Embodiments are given for chips with both hole and electron mobility increased in different transistors, and a method for making such a transistor or chip.

What is claimed is: 
     
       1. A semiconductor chip comprising:
 a first n-type transistor having a first channel and a first gate stack in contact with a surface of the first channel, the first channel comprising a first nanowire having a length l 1  along a first orientation of a crystal structure of the semiconductor chip and a thickness t C1 , wherein the thickness t C1  is less than or equal to about 20 nanometers; and 
 a second p-type transistor having a second channel and a second gate stack in contact with a surface of the second channel, the second channel comprising a second nanowire having a length l 2  along a second orientation of a crystal structure of the semiconductor chip and a thickness t C2 , wherein the thickness t C2  is less than or equal to about 20 nanometers; 
 wherein: 
 the first gate stack exerts a tensile force on the contacted surface of the first channel such that electrical mobility of carriers along the first channel length l 1  is increased due to the tensile force in dependence on the first orientation; and 
 the second gate stack exerts a compressive force on the contacted surface of the second channel such that electrical mobility of carriers along the second channel length l 2  is increased due to the compressive force in dependence on the second orientation wherein the first orientation is substantially along a <100> Miller index and the second orientation is substantially along a <110> Miller index. 
 
     
     
       2. The semiconductor chip of  claim 1 , wherein the semiconductor chip, the first channel and the second channel comprise silicon. 
     
     
       3. The semiconductor chip of  claim 1 , wherein the first gate stack comprises a gate dielectric film and a gate, wherein at least one of:
 the gate dielectric is selected from the set {tensile oxynitride and hafnium oxide}; and 
 the gate is selected from the set {titanium nitride, tantalum nitride and tensile polysilicon}. 
 
     
     
       4. The semiconductor chip of  claim 3 , wherein the second gate stack comprises a gate dielectric film and a gate, wherein at least one of:
 the gate dielectric is selected from the set {thermal oxide and compressive oxynitride}; and 
 the gate comprises polysilicon.