Inventor · disambiguated record
Paul Armand Asentista Calo
Also filed as: CALO PAUL ARMAND · CALO PAUL ARMAND ASENTISTA
14 granted patents·4 pending applications·28 citations·filing 2005–2023
87Inventor score
Files withINFINEON TECHNOLOGIES AG11FAIRCHILD SEMICONDUCTOR3JEREZA ARMAND VINCENT C2ALMAGRO ERWIN IAN V1INFINEON TECHNOLOGIES AUSTRIA AG1
Top patents by PatentIndex Score
18 records- 0184US8222718B2Semiconductor die package and method for making the sameJEREZA ARMAND VINCENT C·Filed 2009·Granted Jul 17, 2012·12 cites·17 claims
- 0276US12132017B2Method of soldering a semiconductor chip to a chip carrierINFINEON TECHNOLOGIES AG·Filed 2023·Granted Oct 29, 2024·0 cites·18 claims
- 0372US8497164B2Semiconductor die package and method for making the sameJEREZA ARMAND VINCENT C·Filed 2012·Granted Jul 30, 2013·3 cites·17 claims
- 0472US7402462B2Folded frame carrier for MOSFET BGAFAIRCHILD SEMICONDUCTOR·Filed 2005·Granted Jul 22, 2008·8 cites·26 claims
- 0568US11830835B2Chip with chip pad and associated solder flux outgassing trenchINFINEON TECHNOLOGIES AG·Filed 2021·Granted Nov 28, 2023·0 cites·11 claims
- 0666US7586179B2Wireless semiconductor package for efficient heat dissipationFAIRCHILD SEMICONDUCTOR·Filed 2007·Granted Sep 8, 2009·4 cites·13 claims
- 0756US9640459B1Semiconductor device including a solder barrierINFINEON TECHNOLOGIES AG·Filed 2016·Granted May 2, 2017·1 cites·20 claims
- 0855US11274984B2Pressure sensor having a lidless/laminate structureINFINEON TECHNOLOGIES AG·Filed 2020·Granted Mar 15, 2022·0 cites·16 claims
- 0954US12094807B2Stacked transistor chip package with source couplingINFINEON TECHNOLOGIES AG·Filed 2021·Granted Sep 17, 2024·0 cites·16 claims
- 1053US2023095545A1Semiconductor Packages and Methods for Manufacturing ThereofINFINEON TECHNOLOGIES AG·Filed 2022·Application pending·0 cites
- 1151US2023230903A1Semiconductor chip, chip system, method of forming a semiconductor chip, and method of forming a chip systemINFINEON TECHNOLOGIES AG·Filed 2022·Application pending·0 cites
- 1250US2022375883A1Method for Fabricating an Electrical Device Package Comprising Plateable Encapsulating LayersINFINEON TECHNOLOGIES AG·Filed 2022·Application pending·0 cites
- 1349US12218038B2Leadframe, semiconductor package and methodINFINEON TECHNOLOGIES AUSTRIA AG·Filed 2019·Granted Feb 4, 2025·0 cites·20 claims
- 1449US2022278085A1Method for connecting an electrical device to a bottom unit by using a solderless jointINFINEON TECHNOLOGIES AG·Filed 2022·Application pending·0 cites
- 1548US7800207B2Method for connecting a die attach pad to a lead frame and product thereofFAIRCHILD SEMICONDUCTOR·Filed 2007·Granted Sep 21, 2010·0 cites·14 claims
- 1647US11211356B2Power semiconductor package and method for fabricating a power semiconductor packageINFINEON TECHNOLOGIES AG·Filed 2020·Granted Dec 28, 2021·0 cites·17 claims
- 1744US11355429B2Electrical interconnect structure with radial spokes for improved solder void controlINFINEON TECHNOLOGIES AG·Filed 2020·Granted Jun 7, 2022·0 cites·10 claims
- 1838US8110492B2Method for connecting a die attach pad to a lead frame and product thereofALMAGRO ERWIN IAN V·Filed 2010·Granted Feb 7, 2012·0 cites·2 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →