Inventor · disambiguated record
Paul Alexander Cunningham
Also filed as: CUNNINGHAM PAUL · CUNNINGHAM PAUL A · CUNNINGHAM PAUL ALEXANDER
16 granted patents·3 pending applications·114 citations·filing 1988–2015
92Inventor score
Top patents by PatentIndex Score
19 records- 0193US9606179B1Method and system for improving efficiency of XOR-based test compression using an embedded serializer-deserializerCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Mar 28, 2017·7 cites·18 claims
- 0290US9513335B1Method for using XOR trees for physically efficient scan compression and decompression logicCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Dec 6, 2016·5 cites·10 claims
- 0390US9501590B1Systems and methods for testing integrated circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Nov 22, 2016·9 cites·11 claims
- 0490US9470756B1Method for using sequential decompression logic for VLSI test in a physically efficient constructionCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Oct 18, 2016·5 cites·20 claims
- 0587US9817068B1Method and system for improving efficiency of sequential test compression using overscanCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Nov 14, 2017·4 cites·12 claims
- 0687US9465896B1Systems and methods for testing integrated circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Oct 11, 2016·6 cites·13 claims
- 0786US9470754B1Elastic compression-optimizing tester bandwidth with compressed test stimuli using overscan and variable serializationCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Oct 18, 2016·3 cites·20 claims
- 0880US9817069B1Method and system for construction of a highly efficient and predictable sequential test decompression logicCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Nov 14, 2017·2 cites·20 claims
- 0977US9470755B1Method for dividing testable logic into a two-dimensional grid for physically efficient scanCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Oct 18, 2016·2 cites·20 claims
- 1074US4933534AElectrical heater and plugCUNNINGHAM PAUL A·Filed 1988·Granted Jun 12, 1990·40 cites·22 claims
- 1166US7095251B2Clock gating for synchronous circuitsAZURO UK LTD·Filed 2004·Granted Aug 22, 2006·12 cites·26 claims
- 1254US7131090B2Clocked gating based on measured performanceAZURO UK LTD·Filed 2004·Granted Oct 31, 2006·4 cites·27 claims
- 1350US6976232B2Method of designing and making an integrated circuitAZURO UK LTD·Filed 2003·Granted Dec 13, 2005·2 cites·14 claims
- 1447US6831482B2Control of guard-flopsAZURO UK LTD·Filed 2003·Granted Dec 14, 2004·4 cites·13 claims
- 1545US7194708B2Generation of clock gating function for synchronous circuitAZURO UK LTD·Filed 2004·Granted Mar 20, 2007·0 cites·24 claims
- 1643US2004153977A1Clock gating for hierarchical structureFiled 2004·Application pending·0 cites
- 1743US2004230923A1Generation of improved input function for clocked element in synchronous circuitFiled 2004·Application pending·0 cites
- 1836US2007288875A1Skew clock treeAZURO UK LTD·Filed 2006·Application pending·0 cites
- 1935US4995835AElectrical heater and plugCUNNINGHAM PAUL A·Filed 1989·Granted Feb 26, 1991·9 cites·24 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →