Inventor · disambiguated record
Paul A. Grudowski
Also filed as: GRUDOWSKI PAUL · GRUDOWSKI PAUL A · GRUDOWSKI PAUL ALEXANDER
29 granted patents·9 pending applications·499 citations·filing 2001–2020
96Inventor score
Top patents by PatentIndex Score
38 records- 0196US7416605B2Anneal of epitaxial layer in a semiconductor deviceFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Aug 26, 2008·109 cites·26 claims
- 0295US6369430B1Method of preventing two neighboring contacts from a short-circuit caused by a void between them and device having the sameMOTOROLA INC·Filed 2001·Granted Apr 9, 2002·121 cites·14 claims
- 0393US6864135B2Semiconductor fabrication process using transistor spacers of differing widthsFREESCALE SEMICONDUCTOR INC·Filed 2002·Granted Mar 8, 2005·82 cites·19 claims
- 0491US7132704B2Transistor sidewall spacer stress modulationFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Nov 7, 2006·14 cites·18 claims
- 0589US6902971B2Transistor sidewall spacer stress modulationFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Jun 7, 2005·48 cites·13 claims
- 0687US7736957B2Method of making a semiconductor device with embedded stressorFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Jun 15, 2010·20 cites·19 claims
- 0787US7420202B2Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic deviceFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Sep 2, 2008·13 cites·12 claims
- 0884US7491630B2Undoped gate poly integration for improved gate patterning and cobalt silicide extendibilityFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Feb 17, 2009·11 cites·20 claims
- 0983US7402472B2Method of making a nitrided gate dielectricFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Jul 22, 2008·9 cites·11 claims
- 1080US7442598B2Method of forming an interlayer dielectricFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Oct 28, 2008·10 cites·15 claims
- 1179US7511360B2Semiconductor device having stressors and method for formingFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Mar 31, 2009·6 cites·12 claims
- 1276US7538002B2Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressorsFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted May 26, 2009·7 cites·20 claims
- 1376US7504289B2Process for forming an electronic device including transistor structures with sidewall spacersFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Mar 17, 2009·7 cites·7 claims
- 1475US7714318B2Electronic device including a transistor structure having an active region adjacent to a stressor layerFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted May 11, 2010·5 cites·20 claims
- 1575US7687354B2Fabrication of a semiconductor device with stressorFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Mar 30, 2010·6 cites·20 claims
- 1675US7579228B2Disposable organic spacersFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Aug 25, 2009·5 cites·20 claims
- 1774US8980734B2Gate security featureFREESCALE SEMICONDUCTOR INC·Filed 2013·Granted Mar 17, 2015·3 cites·14 claims
- 1871US10580906B1Semiconductor device comprising a PN junction diodeNXP BV·Filed 2018·Granted Mar 3, 2020·2 cites·15 claims
- 1971US7528029B2Stressor integration and method thereofFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted May 5, 2009·6 cites·20 claims
- 2071US7214590B2Method of forming an electronic deviceFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted May 8, 2007·5 cites·20 claims
- 2169US7678698B2Method of forming a semiconductor device with multiple tensile stressor layersFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Mar 16, 2010·3 cites·18 claims
- 2268US7843011B2Electronic device including insulating layers having different strainsFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Nov 30, 2010·2 cites·20 claims
- 2357US6846716B2Integrated circuit device and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Jan 25, 2005·5 cites·5 claims
- 2449US9847389B2Semiconductor device including an active region and two layers having different stress characteristicsWINSTEAD BRIAN A·Filed 2013·Granted Dec 19, 2017·0 cites·17 claims
- 2548US8021957B2Process of forming an electronic device including insulating layers having different strainsFREESCALE SEMICONDUCTOR INC·Filed 2010·Granted Sep 20, 2011·0 cites·20 claims
- 2647US8569858B2Semiconductor device including an active region and two layers having different stress characteristicsWINSTEAD BRIAN A·Filed 2006·Granted Oct 29, 2013·0 cites·22 claims
- 2745US7745298B2Method of forming a viaFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Jun 29, 2010·0 cites·4 claims
- 2843US7700499B2Multilayer silicon nitride deposition for a semiconductor deviceFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Apr 20, 2010·0 cites·22 claims
- 2943US2008293192A1Semiconductor device with stressors and methods thereofZOLLNER STEFAN·Filed 2007·Application pending·0 cites
- 3043US2008173908A1Multilayer silicon nitride deposition for a semiconductor deviceFREESCALE SEMICONDUCTOR INC·Filed 2007·Application pending·0 cites
- 3142US2007196988A1Poly pre-doping anneals for improved gate profilesSHROFF MEHUL D·Filed 2006·Application pending·0 cites
- 3241US11222961B2Lateral semiconductor device having raised source and drain, and method of manufacture thererofNXP BV·Filed 2020·Granted Jan 11, 2022·0 cites·15 claims
- 3341US2007049006A1Method for integration of a low-k pre-metal dielectricSPENCER GREGORY·Filed 2005·Application pending·0 cites
- 3439US2008026517A1Method for forming a stressor layerGRUDOWSKI PAUL A·Filed 2006·Application pending·0 cites
- 3536US2011210401A1Multilayer silicon nitride deposition for a semiconductor deviceFREESCALE SEMICONDUCTOR INC·Filed 2010·Application pending·0 cites
- 3636US2006084220A1Differentially nitrided gate dielectrics in CMOS fabrication processFREESCALE SEMICONDUCTOR INC·Filed 2004·Application pending·0 cites
- 3736US2007197011A1Method for improving self-aligned silicide extendibility with spacer recess using a stand-alone recess etch integrationFREESCALE SEMICONDUCTOR INC·Filed 2006·Application pending·0 cites
- 3834US2005156229A1Integrated circuit device and method thereforFiled 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →